The synthesis method of logic circuits based on the RRAM (Resistive Random Access memory) devices is of great concern in recent years. Inspired by the CMOS-like RRAM based logic gates, this work proposes a NMOS-like R...
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The synthesis method of logic circuits based on the RRAM (Resistive Random Access memory) devices is of great concern in recent years. Inspired by the CMOS-like RRAM based logic gates, this work proposes a NMOS-like RRAM gate family. The advantages of the proposed NMOS-like RRAM gates include: (1) all the gate circuits are array-implementable;(2) the gate family is logic complete;(3) the NOR, AND and NOT gates only consume single cycle respectively in the computation phase;(4) the gate circuits save half number of RRAM devices compared with the CMOS-like RRAM based counterparts. Furthermore, the synthesis method of logic circuits based on the NMOS-like RRAM gates is proposed and discussed. The single-cycle NMOS-like RRAM gates are utilized in priority under the constraints of the logic block. The features of the proposed synthesis method are: (1) it generates the high-performance logic circuits because the NMOS-like RRAM based gates work in parallel;(2) the logic block based on the proposed NMOS-like gates can be realized in the RRAM array;(3) the large-scale logic functions can be implemented by cascading the logic blocks. The in-array full-adder circuit generated by the proposed synthesis method only consumes three cycles in minimum, which outperforms the previous RRAM based counterpart. The synthesis results on the benchmark circuits show that the proposed synthesis method is able to generate the high-performance circuit in RRAM arrays for arbitrary logic functions.
computation in memory (CiM) promises to significantly improve the efficiency of data-intensive applications. Spin Transfer Torque (STT) magnetic memory, as one of the front-runners in emerging resistive non-volatile m...
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ISBN:
(纸本)9781665416955
computation in memory (CiM) promises to significantly improve the efficiency of data-intensive applications. Spin Transfer Torque (STT) magnetic memory, as one of the front-runners in emerging resistive non-volatile memories, is a suitable candidate for the implementation of CiM architectures. However, the much smaller off/on ratio of resistance states compared to other non-volatile memories makes CiM implementation challenging in this technology. This is further exacerbated with asymmetrical process and temperature variations of the resistance states of Magnetic Tunnel Junction (MTJs) and CMOS components, resulting in erroneous CiM operations. In this paper, we perform a detailed technology-aware statistical failure analysis of CiM operation and design the optimal reference circuitry for CiM sensing to minimize the failure rate with respect to process and temperature variations. Our results show that using a simpler model of CiM array is sufficient for the optimization of the sensing circuitry. However, it may lead to over-optimistic estimation of failure rates. Therefore, a more comprehensive model is utilized for accurate estimation of CiM failure rates.
作者：
Fengshi TianJingwen JiangJinhao LiangZhiyuan ZhangJiahe ShiChaoming FangHui WuXiaoyong XueXiaoyang ZengSe Key Lborory of ASIC nd Syse
Schoo of Microeecronics Fudn Universiy Shnghi ChinSe Key Lborory of ASIC nd Syse Schoo of Microeecronics Fudn Universiy Shnghi ChinSe Key Lborory of ASIC nd Syse Schoo of Microeecronics Fudn Universiy Shnghi ChinSe Key Lborory of ASIC nd Syse Schoo of Microeecronics Fudn Universiy Shnghi ChinSe Key Lborory of ASIC nd Syse Schoo of Microeecronics Fudn Universiy Shnghi ChinSe Key Lborory of ASIC nd Syse Schoo of Microeecronics Fudn Universiy Shnghi ChinSe Key Lborory of ASIC nd Syse Schoo of Microeecronics Fudn Universiy Shnghi ChinSe Key Lborory of ASIC nd Syse Schoo of Microeecronics Fudn Universiy Shnghi ChinSe Key Lborory of ASIC nd Syse Schoo of Microeecronics Fudn Universiy Shnghi Chin
EMG based hand gesture recognition on convolutional neural networks (CNNs) has been widely learned, which gains high accuracy. However, CNN based systems are computationally complex and power consuming, thus hard to b...
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ISBN:
(数字)9781665484855
ISBN:
(纸本)9781665484862
EMG based hand gesture recognition on convolutional neural networks (CNNs) has been widely learned, which gains high accuracy. However, CNN based systems are computationally complex and power consuming, thus hard to be deployed at edge. Biologically inspired, a new neuromorphic learning and computing approach for electromyogram (EMG) based hand gesture recognition tasks is proposed in this work. This approach designs an activate and inhibit joint processing spiking neural network (AIPS-SNN) which reaches an accuracy of 85.6% on Nina Pro dataset. Furthermore, the AIPS-SNN is deployed on the proposed memristor based computation in-memory (CIM) system, the power efficiency and area efficiency of which reach 10.146 TOPS/W and 35.399 GOPS/mm~2, respectively. The experimental results indicate that the proposed neuromorphic CIM engine is promising for edge deployment.
We propose a novel computation-in-memory (CIM) architecture based on DRAM for binary neural network, in which a novel charge sharing circuit enables us to perform all logic operations and accumulation inside sub-array...
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ISBN:
(纸本)9781728163475
We propose a novel computation-in-memory (CIM) architecture based on DRAM for binary neural network, in which a novel charge sharing circuit enables us to perform all logic operations and accumulation inside sub-array at a very small area overhead (1.22%). Especially, the in-DRAM accumulation can significantly reduce off-chip DRAM accesses. Our experiments show that, on VGG-9 model for CIFAR-10, our proposed method, realized on DDR4 DRAM, gives 2.56 times smaller latency per image and 19.57 times lower energy consumption in off-chip data transfer than the existing methods, modified Ambit and DRISA, at a very small accuracy loss (0.23%).
In this paper, memristor based computation-in-memory (CiM) architecture is introduced to mitigate today's challenges faced with the conventional CMOS technologies and von Neumann architecture due to the emergence ...
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ISBN:
(纸本)9781728151601
In this paper, memristor based computation-in-memory (CiM) architecture is introduced to mitigate today's challenges faced with the conventional CMOS technologies and von Neumann architecture due to the emergence of Big data era. Memristor material has shown through design and simulation as presented in this paper where necessary to have high switching speed, non-volatile capability, compact density using crossbar array, chaotic and non-binary ability, almost zero power and current leakage thus making memristor-based computation-in-memory architecture the needed technology revolution to mitigate these Big data computing limits caused by the conventional computer architecture and CMOS process technologies. The CMOS technologies and von Neumann architecture have reached fabrication physical limit as transistor scaling goes below 45nm technology node thus resulting to increasing delays that occur in the metal interconnect for signal propagation in transistors, power leakages, low data reliability, security issues, and high cost of developing and building CMOS chip-fabrication facilities as scaling goes down below 45nm.
Neuromorphic RRAM has become the most promising candidate for AI applications. But it suffers three issues including degradation, defects and errors. To overcome the three issues we proposed a precompensation techniqu...
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ISBN:
(纸本)9781538694664
Neuromorphic RRAM has become the most promising candidate for AI applications. But it suffers three issues including degradation, defects and errors. To overcome the three issues we proposed a precompensation technique for compensating resistive degradation. A linear-system-based BIST architecture is developed with proposed diagonal sliding march test can effectively and efficiently screen out the uncompensated degradation and permanent defects. Analog Berger codes is proposed for detecting transient errors for variation learning and self-checking for asymmetric errors. From evaluations, the precompensation takes only 5/B time for batch operations of B cycles. Proposed BIST approach and method can reduced 2LN march tests to 6N for L-level RRAMs. The self-healing ability is verified by analog-Berger-code error detection. From experiments using a typical neural network for MNIST handwritten digit dataset the network can be healed with only 2% of accuracy and about 35% of training steps.
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