Current High-Level synthesis (HLS) tools perform excellently for the synthesis of computationkernels, but they often don't optimize memory bandwidth. As memory access is a bottleneck in many algorithms, the perfo...
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ISBN:
(纸本)9783981537024
Current High-Level synthesis (HLS) tools perform excellently for the synthesis of computationkernels, but they often don't optimize memory bandwidth. As memory access is a bottleneck in many algorithms, the performance of the generated circuit will benefit substantially from memory access optimization. In this paper we present an automated method and a toolchain to detect reuse of array data in loop nests and to build hardware that exploits this data reuse. This saves memory bandwidth and improves circuit performance. We make use of the polyhedral representation of the source program, which makes our method computationally easy. Our software complements the existing HLS flows. Starting from a loop nest written in C, our tool generates a reuse buffer and a loop controller, and preprocesses the loop body for synthesis with an existing HLS tool. Our automated tool produces designs from unoptimized source code that are as efficient as those generated by a commercial HLS tool from manually-optimized source code.
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