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CREW: computation reuse and efficient weight storage for hardware-accelerated MLPs and RNNs

JOURNAL OF SYSTEMS ARCHITECTURE 2022年 129卷

作者： Riera, Marc Arnau, Jose Maria Gonzalez, Antonio Univ Politecn Catalunya UPC Barcelona Spain

Deep Neural Networks (DNNs) have achieved tremendous success for cognitive applications. The core operation in a DNN is the dot product between quantized inputs and weights. Prior works exploit the weight/input repetition that arises due to quantization to avoid redundant computations in Convolutional Neural Networks (CNNs). However, in this paper we show that their effectiveness is severely limited when applied to FullyConnected (FC) layers, which are commonly used in state-of-the-art DNNs, as it is the case of modern Recurrent Neural Networks (RNNs) and Transformer models. To improve energy-efficiency of FC computation we present CREW, a hardware accelerator that implements computation reuse and an Efficient Weight Storage mechanism to exploit the large number of repeated weights in FC layers. CREW first performs the multiplications of the unique weights by their respective inputs and stores the results in an on-chip buffer. The storage requirements are modest due to the small number of unique weights and the relatively small size of the input compared to convolutional layers. Next, CREW computes each output by fetching and adding its required products. To this end, each weight is replaced offline by an index in the buffer of unique products. Indices are typically smaller than the quantized weights, since the number of unique weights for each input tends to be much lower than the range of quantized weights, which reduces storage and memory bandwidth requirements. Overall, CREW greatly reduces the number of multiplications and provides significant savings in model memory footprint and memory bandwidth usage. We evaluate CREW on a diverse set of modern DNNs. On average, CREW provides 2.61x speedup and 2.42x energy savings over a TPU-like accelerator. Compared to UCNN, a state-of-art computation reuse technique, CREW achieves 2.10x speedup and 2.08x energy savings on average.

关键词： Machine learning Deep neural networks computation reuse Accelerators Low energy

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Energy-efficient acceleration of convolutional neural networks using computation reuse

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JOURNAL OF SYSTEMS ARCHITECTURE 2022年 126卷

作者： Ghanbari, Azam Modarressi, Mehdi Univ Tehran Coll Engn Sch Elect & Comp Engn Tehran Iran

The large and ever-increasing size of state-of-the-art convolutional neural networks (CNNs) poses both throughput and energy challenges to the underlying hardware, especially in embedded and mobile computing platforms. Weight quantization is a promising method to reduce the computational complexity of neural networks without losing significant accuracy. In this paper, we show that the value locality of quantized filter weights brings about a high amount of computation redundancy in CNNs. In order to leverage this computational redundancy to reduce neural network complexity, this paper proposes CORN-C, a computation reuse-aware accelerator for CNNs. CORN-C leverages two opportunities to eliminate repetitive computations: (1) the specific algorithmic structure of the convolutional neural networks in which each element of the input data (and intermediate feature maps) is multiplied by tens to thousands of CNN filter weights, and (2) the data value locality in the network filter weights when low-precision quantization is applied. Experimental results show that by eliminating the considerable amount of repetitive multiplication, computation reuse offers up to 10.5%-20.9% energy reduction and 13.4%-41.6% latency reduction over state-of-the-art accelerators across a set of widely used CNN benchmarks.

关键词： Convolutional neural networks computation reuse Energy-efficiency Quantization Hardware acceleration

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Adaptive computation reuse for Energy-Efficient Training of Deep Neural Networks

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ACM Transactions on Embedded Computing Systems 2021年第6期20卷 1–24页

作者： Jason Servais Ehsan Atoofian Lakehead University Canada

In recent years, Deep Neural Networks (DNNs) have been deployed into a diverse set of applications from voice recognition to scene generation mostly due to their high-accuracy. DNNs are known to be computationally intensive applications, requiring a significant power budget. There have been a large number of investigations into energy-efficiency of DNNs. However, most of them primarily focused on inference while training of DNNs has received little *** work proposes an adaptive technique to identify and avoid redundant computations during the training of DNNs. Elements of activations exhibit a high degree of similarity, causing inputs and outputs of layers of neural networks to perform redundant computations. Based on this observation, we propose Adaptive computation reuse for Tensor Cores (ACRTC) where results of previous arithmetic operations are used to avoid redundant computations. ACRTC is an architectural technique, which enables accelerators to take advantage of similarity in input operands and speedup the training process while also increasing energy-efficiency. ACRTC dynamically adjusts the strength of computation reuse based on the tolerance of precision relaxation in different training phases. Over a wide range of neural network topologies, ACRTC accelerates training by 33% and saves energy by 32% with negligible impact on accuracy.

关键词： computation reuse training DNNs accelerator energy performance

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AxR-NN: Approximate computation reuse for Energy-Efficient Convolutional Neural Networks 20

AxR-NN: Approximate Computation Reuse for Energy-Efficient C...

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Proceedings of the 2020 on Great Lakes Symposium on VLSI

作者： Dongning Ma Xunzhao Yin Michael Niemier X. Sharon Hu Xun Jiao Villanova University Villanova PA USA Zhejiang University Hangzhou China University of Notre Dame Notre Dame IN USA

ISBN: (纸本)9781450379441

The recent success of convolutional neural networks (CNN) has led its implementation in specialized accelerators such as graphics processing unit (GPUs). However, the intensive computing workloads of CNNs remain a challenge to existing accelerators. By leveraging the error tolerance of CNNs, we propose a novel method to design energy-efficient CNN accelerators using approximate computation reuse (ACR), referred to as AxRNN. computation reuse aims to reuse the previously computed results to avoid redundant executions. However, it cannot be applied directly to CNNs because CNNs do not have enough data locality. Thus, AxRNN performs approximate computation reuse under relaxed precision requirements on input patterns and design a reconfigurable architecture to support the ACR. This reconfigurable pattern matching is central to achieve a "controllable approximation". We implement the AxRNN using content addressable memory and integrate them with floating point units. Simulation results show that AxRNN reduces the computation energy by 30-58% with only 1-2.5% accuracy degradation on MNIST, EMNIST, and CIFAR-10 dataset.

关键词： content addressable memory computation reuse neural networks

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Complexity reduction of digital filters using shift inclusive differential coefficients

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2004年第6期52卷 1760-1772页

作者： Choo, HS Muhammad, K Roy, K Purdue Univ Sch Elect & Comp Engn Low Power VLSI Lab W Lafayette IN 47907 USA Texas Instruments Inc Dallas TX 75243 USA

We present a graph theoretical methodology that reduces the implementation complexity of the multiplication of a constant vector and a scalar. The complexity of implementation is defined as the required amount of computations like additions. The proposed approach is called minimally redundant parallel (MRP) optimization and is mainly presented in a finite impluse response (FIR) filtering framework to obtain a low-complexity multiplierless implementation. The key idea is to expand the design space using shift inclusive differential coefficients (SIDCs) together with computation reordering using a graph theoretic approach to obtain maximal computation sharing. The problem is formulated using a graph in which vertices and edges represent coefficients and computational cost (number of resources). The multiplierless solution is obtained by solving a set cover problem on the vertices in the graph. A simple polynomial run time algorithm based on a greedy approach is presented. The proposed approach is compared with common-subexpression elimination to show slightly better results and is combined with it for further reduction of complexity. Simulation results show that 50-60% complexity reduction is achieved by only applying the MRP algorithm, and 70% complexity reduction is obtainable by combining it with common-subexpression elimination under a delay constraint of two or three.

关键词： complexity reduction computation reuse digital filter filter design high-level synthesis low-complexity low-power

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A graph theoretic approach for synthesizing very low-complexity high-speed digital filters

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2002年第2期21卷 204-216页

作者： Muhammad, K Roy, K Texas Instruments Inc Dallas TX 75243 USA Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

We present computation reduction techniques which can either be used to obtain multiplierless implementation of finite impulse response (FIR) digital filters or to further improve multiplierless implementation obtained by currently used techniques. Although presented in the FIR filtering framework, these ideas are also directly applicable to any task/application which can be expressed as multiplication of vectors by scalars. The presented approach is to remove computational redundancy by reordering computation. The reordering problem is formulated using a graph in which vertices represent coefficients and edges represent resources required in a computation using the differential coefficient defined by the difference of the vertices joined by the edge. This interpretation leads to various methods for computation reduction for which simple polynomial run time algorithms are presented. It is shown that about 20% reduction in the number of add operations per coefficient can be obtained over the conventional multiplierless implementations. It is also shown that implementations requiring less than one adder per coefficient can be obtained using the presented approaches when using nonuniformly scaled coefficients quantized from infinite precision representation by simple rounding.

关键词： computation reuse digital filters high-level synthesis high-performance low-complexity low-power system-level

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A Low-Power Motion Estimation Architecture for HEVC Based on a New Sum of Absolute Difference computation

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2020年第1期30卷 243-255页

作者： Jia, Luheng Tsui, Chi-Ying Au, Oscar C. Jia, Kebin Beijing Univ Technol Fac Informat Technol Beijing 100124 Peoples R China Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Peoples R China Hong Kong Univ Sci & Technol Hong Kong Peoples R China Origin Wireless Inc Greenbelt MD 20770 USA

High-efficiency video coding (HEVC) poses a considerable challenge to hardware implementation due to its complexity. Mobile devices are powered by batteries that are limited in capacity. Therefore, reducing the power consumption arising from the implementation of sophisticated coding tools in HEVC is an especially important issue for mobile devices. In particular, motion estimation (ME) is the major contributor to the power consumption of the encoder and the calculation of the sum of absolute difference (SAD) for ME consumes more than 50% of the total ME power. In this paper, a low-power motion estimation VLSI architecture is proposed based on a novel method of calculating the SAD. By reusing the calculation, the computation complexity and, hence, the power consumption are reduced. A low-power systolic processing elements array and a novel memory hierarchy are developed, which enable real-time processing of 8K resolution video with only half of the power consumption when compared with the state-of-the-art design.

关键词： HEVC ME SAD low-power computation reuse

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ICedge: When Edge Computing Meets Information-Centric Networking

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IEEE INTERNET OF THINGS JOURNAL 2020年第5期7卷 4203-4217页

作者： Mastorakis, Spyridon Mtibaa, Abderrahmen Lee, Jonathan Misra, Satyajayant Univ Nebraska Dept Comp Sci Omaha NE 68182 USA Univ Missouri Dept Math & Comp Sci St Louis MO 63103 USA Duke Univ Dept Comp Sci Durham NC 27708 USA New Mexico State Univ Dept Comp Sci Las Cruces NM 88003 USA

In today's era of explosion of Internet of Things (IoT) and end-user devices and their data volume emanating at the network's edge, the network should be more in-tune with meeting the needs of these demanding edge computing applications. To this end, we design and prototype Information-Centric edge (ICedge), a general-purpose networking framework that streamlines service invocation and improves the reuse of redundant computation at the edge. ICedge runs on top of named-data networking, a realization of the information-centric networking vision, and handles the "low-level" network communication on behalf of applications. ICedge features a fully distributed design that: 1) enables users to get seamlessly on-boarded onto an edge network;2) delivers application invoked tasks to edge nodes for execution in a timely manner;and 3) offers naming abstractions and network-based mechanisms to enable (partial or full) reuse of the results of already executed tasks among users, which we call "compute reuse," resulting in lower task completion times and efficient use of edge computing resources. Our simulation and testbed deployment results demonstrate that ICedge can achieve up to 50x lower task completion times leveraging its network-based compute reuse mechanism compared to cases, where reuse is not available.

关键词： computation reuse edge computing information-centric networking Internet of Things (IoT) named-data networking service discovery service invocation

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SLID: Exploiting Spatial Locality in Input Data as a computational reuse Method for Efficient CNN

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IEEE ACCESS 2021年 9卷 57179-57187页

作者： Alantali, Fatmah Halawani, Yasmin Mohammad, Baker Al-Qutayri, Mahmoud Khalifa Univ Dept Elect & Comp Engn Syst On Chip Ctr SoCC Abu Dhabi U Arab Emirates

Convolutional Neural Networks (CNNs) revolutionized computer vision and reached the state-of-the-art performance for image processing, object recognition, and video classification. Even though CNN inference is notoriously compute-intensive, as convolutions account for >90% of the total operation tasks, the ability to tradeoff between accuracy, performance, power, and latency to meet target application makes it an open research topic. This paper proposes the Spatial Locality Input Data (SLID) method for computational reuse during the inference stage for a pre-trained network. The method exploits input data spatial locality via skipping partial processing of the multiply-and-accumulate (MAC) operations for adjacent data and equating its value to previously computed ones. SLID improves the throughput of resource-constrained devices (Internet-of-Things, edge devices) and accelerates computations during the inference phase by reducing the number of MAC operations. Such approximate computing schema does not require a similarity quantification step nor any modification for the training stage. The computational data reuse was evaluated on three well-known distinctive CNN structures and data sets with alternating layer selections: LeNet, CIFAR-10, and AlexNet. The computational data reuse method saves up to 34.9%, 49.84%, and 31.5% of MAC operations while reducing the accuracy by 8%, 3.7%, and 5.0% for the three models mentioned earlier, respectively. Besides, the proposed method saves on memory access by eliminating data fetching of skipped inputs. Furthermore, filter size, strides, and padding on the accuracy and savings of operations are analyzed. SLID is the first work to exploit the input spatial locality for savings on CNN convolution operations with minimal accuracy loss and without memory or computational overhead. This makes it a great option to support intelligence at the edge.

关键词： Hardware Face recognition Licenses Kernel computational modeling Acceleration Two dimensional displays CNN accelerator computation reuse input similarity approximate computing in-memory computing RRAM

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Efficient Video Privacy Protection Against Malicious Face Recognition Models

IEEE OPEN JOURNAL OF THE COMPUTER SOCIETY

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IEEE OPEN JOURNAL OF THE COMPUTER SOCIETY 2022年第1期3卷 271-280页

作者： Guo, Enting Li, Peng Yu, Shui Wang, Hao Univ Aizu Sch Comp Sci & Engn Aizu Wakamatsu 9658580 Japan Univ Technol Sydney Sch Comp Sci Ultimo NSW 2007 Australia Norwegian Univ Sci & Technol Dept Comp Sci N-7034 Trondheim Norway

The proliferation of powerful facial recognition systems poses a serious threat to user privacy. Attackers could train highly accurate facial recognition models using public data on social platforms. Therefore, recent works have proposed image pre-processing techniques to protect user privacy. Without affecting people's normal viewing, these techniques add special noises into images, so that it would be difficult for attackers to train models with high accuracy. However, existing protection techniques are mainly designed for image data protection, and they cannot be directly applied for video data because of high computational overhead. In this paper, we propose an efficient protection method for video privacy that exploits unique features of video protection to eliminate computation redundancy for computational acceleration. The evaluation results under various benchmarks demonstrate that our method significantly outperforms the traditional methods by reducing computation overhead by 35.5%.

关键词： computation reuse deep learning video privacy

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