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16th International Symposium on System-on-Chip (SoC)

作者： Shibata, Yuuki Tsumura, Takanori Tsumura, Tomoaki Nakashima, Yasuhiko Nagoya Inst Technol Showa Ku Nagoya Aichi 466 Japan Nara Inst Sci & Technol Ikoma Nara Japan

ISBN: (纸本)9781479968909

We have proposed a processor called Auto-Memoization Processor which is based on computation reuse. Until now, we have implemented the auto-memoization mechanism on a single-issue non-pipelined SPARC processor and studied the processor. The processor dynamically detects functions and loop iterations as reusable blocks, and memoizes them automatically. In addition, the processor can apply computation reuse to the blocks with a little reuse overhead. However, the fine evaluation result of the processor may not guarantee enough practicality. This is because instead of such a simple architecture, superscalar architectures are now widely used for generic processors for PCs, embedded processors, and other various processors. Hence, we examine problems which will be caused in the case of implementing the auto-memoization mechanism on an ARM-based superscalar processor and design the ARM-based Auto-Memoization Processor. For example, one of such problems is that pipeline stalls are caused because of the reuse overhead. To solve this problem, we implement a mechanism for overlapping the reuse overhead and the pipeline execution of the processor. The evaluation result with SPEC CPU95 benchmark suite shows that the ARM-based Auto-Memoization Processor can also achieve speed-up as well as the previous SPARC-based Auto-Memoization Processor. In this paper, we describe the implementation and the evaluation result of the ARM-based Auto-Memoization Processor.

关键词： microprocessor architecture computation reuse memoization Auto-Memoization Processor superscalar

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Skipping CNN Convolutions Through Efficient Memoization 19th

Skipping CNN Convolutions Through Efficient Memoization

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19th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

作者： de Moura, Rafael Fao Santos, Paulo C. de Lima, Joao Paulo C. Alves, Marco A. Z. Beck, Antonio C. S. Carro, Luigi Univ Fed Rio Grande do Sul Informat Inst Porto Alegre RS Brazil Univ Fed Parana Dept Informat Curitiba Parana Brazil

ISBN: (纸本)9783030275624;9783030275617

Convolutional Neural Networks (CNNs) have become a de-facto standard for image and video recognition. However, current software and hardware implementations targeting convolutional operations still lack embracing energy budget constraints due to the CNN intensive data processing behavior. This paper proposes a software-based memoization technique to skip entire convolution calculations. We demonstrate that, by grouping output values within proximity-based clusters, it is possible to reduce by hundreds of times the amount of memory necessary to store all the tables. Also, we present a table mapping scheme to index the input set of each convolutional layer to its output value. Our experimental results show that for a YOLOv3-tiny CNN, it is possible to achieve a speedup up to 3.5x while reducing the energy consumption to 22% of the baseline with an accuracy loss of 7.4%.

关键词： Convolutional Neural Networks computation reuse Memoization

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Aggressive Energy Reduction for Video Inference with Software-only Strategies

Aggressive Energy Reduction for Video Inference with Softwar...

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Embedded Systems Week / Int Conf on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) / International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) / Int Conf on Embedded Software (EMSOFT)

作者： Goncalves, Larissa Rozales De Moura, Rafael Fao Carro, Luigi Univ Fed Rio Grande do Sul Porto Alegre RS Brazil

In the past years, several works have proposed custom hardware and software-based techniques for the acceleration of Convolutional Neural Networks (CNNs). Most of these works focus on saving computations by changing the used precision or modifying frame processing. To reach a more aggressive energy reduction, in this paper we propose software-only modifications to the CNNs inference process. Our approach exploits the inherent locality in videos by replacing entire frame computations with a movement prediction algorithm. Furthermore, when a frame must be processed, we avoid energy-demanding floating-point operations, and at the same time reduce memory accesses by employing look-up tables in place of the original convolutions. Using the proposed approach, one can reach significant energy gains of more than 25x for security cameras, and 12x for moving vehicles applications, with only small software modifications.

关键词： Convolutional Neural Networks frame predicton computation reuse

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δLTA: Decoupling Camera Sampling from Processing to Avoid Redundant computations in the Vision Pipeline 23

δLTA: Decoupling Camera Sampling from Processing to Avoid R...

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56th IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Taranco, Raul Arnau, Jose-Maria Gonzalez, Antonio Univ Politecn Cataluna Barcelona Spain

ISBN: (纸本)9798400703294

Continuous Vision (CV) systems are essential for emerging applications like Autonomous Driving (AD) and Augmented/Virtual Reality (AR/VR). A standard CV System-on-a-Chip (SoC) pipeline includes a frontend for image capture and a backend for executing vision algorithms. The frontend typically captures successive similar images with gradual positional and orientational variations. As a result, many regions between consecutive frames yield nearly identical results when processed in the backend. Despite this, current systems process every image region at the camera's sampling rate, overlooking the fact that the actual rate of change in these regions could be significantly lower. In thiswork, we introduce delta LTA (delta ont't Look Twice, it'sAlright), a novel frontend that decouples camera frame sampling from backend processing by extending the camera with the ability to discard redundant image regions before they enter subsequent CV pipeline stages delta LTA informs the backend about the image regions that have notably changed, allowing it to focus solely on processing these distinctive areas and reusing previous results to approximate the outcome for similar ones. As a result, the backend processes each image region using different processing rates based on its temporal variation. dLTA features a new Image Signal Processing (ISP) design providing similarity filtering functionality, seamlessly integrated with other ISP stages to incur zero-latency overhead in the worst-case scenario. It also offers an interface for frontend-backend collaboration to fine-tune similarity filtering based on the application requirements. To illustrate the benefits of this novel approach, we apply it to a state-of-the-art CV localization application, typically employed in AD and AR/VR. We show that delta LTA removes a significant fraction of unneeded frontend and backend memory accesses and redundant backend computations, which reduces the application latency by 15.22% and its energy consu

关键词： Image Signal Processor Image Similarity computation reuse

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RAFALE: smaRt and scalable orchestrAtion system For virtuAL network sErvices 22

RAFALE: smaRt and scalable orchestrAtion system For virtuAL ...

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IEEE 22nd International Conference on High Performance Switching and Routing (IEEE HPSR)

作者： Lahlou, Laaziz Bounas, Amina Mohamadi, Houssem Eddine Kara, Nadjia Univ Quebec Ecole Technol Super Dept Software Engn & IT Montreal PQ Canada

ISBN: (纸本)9781665440059

Time-efficient and scalable mechanisms have a significant role in aiding cloud providers to deploy their increasingly complex virtual network services in a seamless manner thanks to Network Function Virtualization (NFV) and Software Defined Networking (SDN) paradigms. Unfortunately, existing state-of-the-art techniques suffer from non-scalability aptitude and often do not converge rapidly towards feasible solutions, although they provide competetive solutions in acceptable execution time for small-scale scenarios. In this paper, we propose RAFALE, a novel approach that formulates the orchestration problem as a graph matching problem and solves it using two exact algorithms. To the best of our knowledge, this is the first work that attempts to tackle the placement and chaining of the VNFs from a different perspective. Experimental results indicate that RAFALE outperforms, in terms of scalability and time-complexity, the well-known VF2 graph matching algorithm and two existing heuristic-based approaches for the placement and chaining of the VNFs.

关键词： Graph matching computation reuse service function chain network function virtualization orchestration resource management

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Acorn: Aggressive Result Caching in Distributed Data Processing Frameworks 10

Acorn: Aggressive Result Caching in Distributed Data Process...

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10th ACM Symposium on Cloud Computing (SoCC)

作者： Ramjit, Lana Interlandi, Matteo Wu, Eugene Netravali, Ravi Univ Calif Los Angeles Los Angeles CA 90024 USA Microsoft Redmond WA USA Columbia Univ New York NY 10027 USA

ISBN: (纸本)9781450369732

Result caching is crucial to the performance of data processing systems, but two trends complicate its use. First, immutable datasets make it difficult to efficiently employ powerful result caching techniques like predicate analysis, since predicate analysis typically requires optimized query plans but generating those plans can be costly with data immutability. Second, increased support for user-defined functions (UDFs), which are treated as black boxes by query engines, hinders aggressive result caching. This paper overcomes these problems by introducing 1) a judicious adaptation of predicate analysis on analyzed query plans that avoids unnecessary query optimization, and 2) a UDF translator that transparently compiles UDFs from general purpose languages into native equivalents. We then present Acorn, a concrete implementation of these techniques in Spark SQL that provides speedups of up to 5 x across multiple benchmark and real Spark graph processing workloads.

关键词： result caching user-defined functions data analytics frameworks materialized views computation reuse

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A Speed-up Technique for an Auto-Memoization Processor by Reusing Partial Results of Instruction Regions

A Speed-up Technique for an Auto-Memoization Processor by Re...

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3rd International Conference on Networking and Computing (ICNC)

作者： Kamimura, Kazutaka Oda, Ryosuke Yamada, Tatsuhiro Tsumura, Tomoaki Matsuo, Hiroshi Nakashima, Yasuhiko Nagoya Inst Technol Showa Ku Nagoya Aichi 466 Japan Nara Inst Sci & Technol Nara 89165 Japan

ISBN: (纸本)9780769548937;9781467346245

We have proposed an auto-memoization processor based on computation reuse. The auto-memoization processor dynamically detects functions and loop iterations as reusable blocks, and memoizes them automatically. In the past model, computation reuse cannot be applied if the current input sequence even differs by only one input value from the past input sequences, since processing results will differ. This paper proposes a new partial reuse model, which can apply computation reuse to the early part of a reusable block as long as the early part of the current input sequence matches one of the past sequences. In addition, in order to acquire sufficient benefit from the partial reuse model, we also propose a technique that reduces the searching overhead for memoization table by partitioning it. The result of the experiment with SPEC CPU95 suite benchmarks shows that the new method improves the maximum speedup from 40.6% to 55.1%, and the average speedup from 10.6% to 22.8%.

关键词： microprocessor architecture computation reuse memoization auto-memoization processor

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A Neural Network-Based ECG Classification Processor With Exploitation of Heartbeat Similarity

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IEEE ACCESS 2019年 7卷 172774-172782页

作者： Wu, Jiaquan Li, Feiteng Chen, Zhijian Pu, Yu Zhan, Mengyuan Zhejiang Univ Inst VLSI Design Hangzhou 310027 Peoples R China Alibaba DAMO Acad Sunnyvale CA 94085 USA Qingdao Univ Affiliated Hosp Qingdao 266000 Peoples R China

This paper presents a neural network based processor with improved computation efficiency, which aims at multiclass heartbeat recognition in wearable devices. A lightweight classification algorithm that integrates both bi-directional long short-term memory (BLSTM) and convolutional neural networks (CNN) is proposed to deliver high accuracy with minimal network scale. To reduce energy consumption of the classification algorithm, the similarity between consecutive heartbeats is exploited to achieve a high degree of computation reuse in hardware architecture. In addition, neural network compression techniques are adopted in the procedure of inference to save hardware resources. Synthesized in the SMIC 40LL CMOS process, the prototype design has a total area of 1.40 mm(2) with 186.2 kB of static random-access memory (SRAM) capacity. Based on the simulation, this processor achieves an average energy efficiency of 3.52 GOPS/mW under 1.1 V supply at 100 MHz frequency. Compared with the design without computation reuse, the proposed processor provides a speedup by 2.58x and an energy dissipation reduction by 61.27% per classification. This work is a valuable exploration of neural network based design for long-term arrhythmia monitoring in daily life.

关键词： computation reuse electrocardiogram (ECG) processor input similarity neural networks

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Domain-Specific Optimization of Signal Recognition Targeting FPGAs

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2011年第2期4卷 17-17页

作者： Demertzi, Melina Diniz, Pedro C. Hall, Mary W. Gilbert, Anna C. Wang, Yi Univ So Calif Dept Comp Sci Los Angeles CA 90089 USA INESC ID Lisbon Portugal Univ Utah Sch Comp Salt Lake City UT 84112 USA Univ Michigan Ann Arbor MI 48109 USA

Domain-specific optimizations on matrix computations exploiting specific arithmetic and matrix representation formats have achieved significant performance/area gains in Field-Programmable Gate Array (FPGA) hardware designs. In this article, we explore the application of data-driven optimizations to reduce both storage and computation requirements to the problem of signal recognition from a known dictionary. By starting with a high-level mathematical representation of a signal recognition problem, we perform optimizations across the layers of the system, exploiting mathematical structure to improve implementation efficiency. Specifically, we use Walsh wavelet packets in conjunction with a BestBasis algorithm to distinguish between spoken digits. The resulting transform matrices are quite sparse, and exhibit a rich algebraic structure that contains significant overlap across rows. As a consequence, dot-product computations of the transform matrix and signal vectors exhibit significant computation reuse, or repeated identical computations. We present an algorithm for identifying this computation reuse and scheduling of the row computations. We exploit this reuse to derive FPGA hardware implementations that reduce the amount of computation for an individual matrix by as much as 6.35x and an average of 2x for a single dot-product unit. The implementation that exploits reuse achieves a 2x computation reduction compared to three concurrently-executing simpler accumulator units with the same aggregate design area and outperforms software implementations on high-end desktop personal computers.

关键词： Design Performance Configurable architectures FPGA signal recognition computation reuse

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reuse-centric k-means configuration

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INFORMATION SYSTEMS 2021年 100卷 101787-101787页

作者： Zhang, Lijun Guan, Hui Ding, Yufei Shen, Xipeng Krim, Hamid Univ Massachusetts Amherst MA 01002 USA Univ Calif Santa Barbara Santa Barbara CA 93106 USA North Carolina State Univ Raleigh NC 27606 USA

K-means configuration is to find a configuration of k-means (e.g., the number of clusters, feature sets) that maximize some objectives. It is a time-consuming process due to the iterative nature of k-means. This paper proposes reuse-centric k-means configuration to accelerate k-means configuration. It is based on the observation that the explorations of different configurations share lots of common or similar computations. Effectively reusing the computations from prior trials of different configurations could largely shorten the configuration time. To materialize the idea, the paper presents a set of novel techniques, including reuse-based filtering, center reuse, and a two-phase design to capitalize on the reuse opportunities on three levels: validation, number of clusters, and feature sets. Experiments on k-means-based data classification tasks show that reuse-centric k-means configuration can speed up a heuristic search-based configuration process by a factor of 5.8, and a uniform search-based attainment of classification error surfaces by a factor of 9.1. The paper meanwhile provides some important insights on how to effectively apply the acceleration techniques to tap into a full potential. (C) 2021 Elsevier Ltd. All rights reserved.

关键词： K-means Algorithm configuration computation reuse

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