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Towards efficient allocation of graph convolutional networks on hybrid computation-in-memory architecture

Science China(Information Sciences) 2021年第6期64卷 112-125页

作者： Jiaxian CHEN Guanquan LIN Jiexin CHEN Yi WANG College of Computer Science and Software Engineering Shenzhen University

Graph convolutional networks(GCNs) have been applied successfully in social networks and recommendation systems to analyze graph data. Unlike conventional neural networks, GCNs introduce an aggregation phase, which is both computation-and memory-intensive. This phase aggregates features from the neighboring vertices in the graph, which incurs significant amounts of irregular data and memory *** emerging computation-in-memory(CIM) architecture presents a promising solution to alleviate the problem of irregular accesses and provide fast near-data processing for GCN applications by integrating both three-dimensional stacked CIM and general-purpose processing units in the system. This paper presents Graph-CIM, which exploits the hybrid CIM architecture to determine the allocation of GCN ***-CIM models the GCN application process as a directed acyclic graph(DAG) and allocates tasks on the hybrid CIM architecture. It achieves fine-grained graph partitioning to capture the irregular characteristics of the aggregation phase of GCN applications. We use a set of representative GCN models and standard graph datasets to evaluate the effectiveness of Graph-CIM. The experimental results show that Graph-CIM can significantly reduce the processing latency and data-movement overhead compared with the representative schemes.

关键词： computation-in-memory graph convolutional networks hybrid architecture scheduling inference accelerator

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Investigation of memory Non-Ideality Impacts on Non-Volatile memory Based computation-in-memory AI Inference by Comprehensive Simulation Platform

Investigation of Memory Non-Ideality Impacts on Non-Volatile...

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IEEE Silicon Nanoelectronics Workshop (SNW)

作者： Higuchi, Kazuhide Matsui, Chihiro Takeuchi, Ken Univ Tokyo Dept Elect Engn & Informat Syst Tokyo Japan

ISBN: (数字)9781665459792

ISBN: (纸本)9781665459792

Non-idealities of non-volatile (NVM) memory devices, DAC, ADC, and bit/word-line (BL/WL) failures of computation-in-memory (CiM) are investigated by a proposed comprehensive simulation platform. Quantization, variation, shift, random defects, and short circuit are applied to weights of convolution layers and input/output data to analyze the non-idealities of elements in CiM. Non-idealities of NVM device assume multi-level cell operation, conductance variation, retention error, device defects, and short/open contact. DAC/ADC non-idealities assume noise, offset, and circuit defects. BL/WL non-idealities assume fabrication error and short-circuits of adjacent lines. The items to be focused on are identified that ADC/DAC noise, data retention of memory devices, and word-line fabrication yield are crucial.

关键词： computation-in-memory NVM ADC DAC

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Edge computation-in-memory for In-situ Classincremental Learning with Knowledge Distillation

Edge Computation-in-Memory for In-situ Classincremental Lear...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Yoshikiyo, Shinsei Misawa, Naoko Matsui, Chihiro Takeuchi, Ken Univ Tokyo Dept Elect Engn & Informat Syst Tokyo Japan

ISBN: (纸本)9781665484855

This paper proposes a computation-in-memory (CiM) architecture for in-situ class-incremental learning. Due to usage change or environmental change, neural network models implemented in edge devices need to be retrained. Retraining on edge devices improves the latency of the retraining and reduces communication traffic, power consumption, and risk of security and privacy issue. The proposed CiM updates only the final fully connected (fc) layer, not the convolution layers. CiM does not need backpropagation and the number of rewrites to nonvolatile memory is small. The proposed CiM realizes knowledge distillation by cooperation of digital processor and CiM and can be retrained even when the old class data are not available. As a result, the accuracy keeps above 80% on CIFAR-10 when the bit precision of convolution and fc layer are 6 bits and 3 bits, respectively and bit-error rate of convolution and fc layers are less than 0.001% and 1%, respectively. In the proposed CiM, cell program during the retraining concentrate on the final fc layer, which is consistent with the characteristics of proposed class-incremental learning where the fc layer tolerates higher BER of memory cells and low bit precision than the convolution layers.

关键词： computation-in-memory in-situ learning class-incremental learning knowledge distillation

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Domain Specific ReRAM computation-in-memory Design Considering Bit Precision and memory Errors for Simulated Annealing

Domain Specific ReRAM Computation-in-Memory Design Consideri...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Misawa, Naoko Taoka, Kenta Matsui, Chihiro Takeuchi, Ken Univ Tokyo Dept Elect Engn & Informat Syst Tokyo Japan

ISBN: (纸本)9781665484855

In this paper, domain specific ReRAM-based computation-in-memory (CiM) design for simulated annealing (SA) is proposed. This paper reveals that the influence of bit precision and memory cell errors of ReRAM CiM on the accuracy for SA depends on the domains of combinatorial optimization problems, such as Max-Cut and Knapsack problems. It is found that Max-Cut problem has smaller circuit structure and is 3-bit higher tolerant of bit precision, but 4% lower bit-error rate (BER) tolerant, compared with Knapsack problem. In this paper, considering the requirements of bit precision and BER from each domain, examples of case studies and design strategy are presented such that ReRAM CiMs are best optimized in terms of reliability and array area of memory cells. Furthermore, the proposed best-optimized ReRAM CiM for Max-Cut problem improves the quality of SA by introducing approximate answers and avoiding local minimum.

关键词： computation-in-memory ReRAM simulated annealing Max-Cut problem Knapsack problem

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MC-CIM: A Reconfigurable computation-in-memory For Efficient Stereo Matching Cost computation 22

MC-CIM: A Reconfigurable Computation-In-Memory For Efficient...

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59th ACM/IEEE Design Automation Conference (DAC) - From Chips to Systems - Learn Today, Create Tomorrow

作者： Yue, Zhiheng Wang, Yabing Liu, Leibo Wei, Shaojun Yin, Shuoyi Tsinghua Univ Beijing Peoples R China

ISBN: (纸本)9781450391429

This paper proposes the design of a computation-in-memory for stereo matching cost computation. The matching cost computation incurs large energy and latency overhead because of frequent memory access. To overcome previous design limitations, this work, named MC-CIM, performs matching cost computation without incurring memory access and introduces several key features. (1) Lightweight balanced computing unit is integrated within cell array to reduce memory access and improve system throughput. (2) Selfoptimized circuit design enables to alter arithmetic operation for matching algorithm in various scenario. (3) Flexible data mapping method and reconfigurable digital peripheral explore maximum parallelism on different algorithm and bit-precision. The proposed design is implemented in 28nm technology and achieves average performance of 277 TOPs/W.

关键词： computation-in-memory 3D perception Stereo Vision Matching Cost Reconfigurable Design

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Application of mathematical morphology operation with memristor-based computation-in-memory architecture for detecting manufacturing defects

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Fundamental Research 2022年第1期2卷 123-130页

作者： Ying Zhou Bin Gao Qingtian Zhang Peng Yao Yiwen Geng Xinyi Li Wen Sun Meiran Zhao Yue Xi Jianshi Tang He Qian Huaqiang Wu School of Integrated Circuits(SIC) Beijing Innovation Center for Future Chips(ICFC)Tsingfiua UniversityBeijingChina Beijing National Research Center for Information Science and Technology(BNRist) Tsinghua UniversityBeijingChina

Mathematical morphology operations are widely used in image processing such as defect analysis in semiconductor manufacturing and medical image *** data-intensive applications have high requirements during hardware implementation that are challenging for conventional hardware platforms such as central processing units(CPUs)and graphics processing units(GPUs).computation-in-memory(CIM)provides a possible solution for highly efficient morphology *** this study,we demonstrate the application of morphology operation with a novel memristor-based auto-detection architecture and demonstrate non-neuromoq)hic computation on a multi-array-based memristor ***-by-pixel logic computations with low parallelism are converted to parallel operations using ***,hardware-implemented computer-integrated manufacturing was used to experimentally demonstrate typical defect detection tasks in integrated circuit(IC)manufacturing and medical image *** addition,we developed a new implementation scheme employing a four-layer network to realize small-object detection with high *** system benchmark based on the hardware measurement results showed significant improvement in the energy efficiency by approximately 358 times and 32 times more than when a CPU and GPU were employed,respectively,exhibiting the advantage of the proposed memristor-based morphology operation.

关键词： Memristor computation-in-memory Mathematical morphology Defect detection

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Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

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JAPANESE JOURNAL OF APPLIED PHYSICS 2023年第SC期62卷 SC1068-SC1068页

作者： Higuchi, Kazuhide Kobayashi, Tomoki Misawa, Naoko Matsui, Chihiro Takeuchi, Ken Univ Tokyo Grad Sch Engn Dept Elect Engn & Informat Syst Bunkyo Ku Tokyo 1138656 Japan

This paper proposes a tiny and error-tolerant convolutional long short-term memory network (ConvLSTM) for event-based vision sensor data processing with computation-in-memory (CiM) that utilizes resistive random-access memory (ReRAM). To handle the event data by ConvLSTM, the type and parameter of event representation are optimized to pre-process event data. To realize tiny and error-tolerant ConvLSTM CiM, reductions of the bit precision and error tolerance in each ConvLSTM layer and weight are considered. On the other hand, reducing the bit precision degrades inference accuracy and error tolerance. ReRAM has non-idealities such as conductance variation and wearing out by Set/Reset cycles that induces bit inversion. Thus, the bit error rate at each Set/Reset cycle is investigated, and the bit precision of the weight is optimized to accept a bit error rate of 0.1% in simulation. The proposed tiny ConvLSTM can reduce the size of memory by 91% compared with non-optimized ConvLSTM for which weight is represented in 32-bit precision.

关键词： event-based vision computation-in-memory ReRAM ConvLSTM event representation

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Comprehensive analysis on error-robustness of FeFET computation-in-memory for hyperdimensional computing

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JAPANESE JOURNAL OF APPLIED PHYSICS 2023年第SC期62卷 SC1053-SC1053页

作者： Matsui, Chihiro Kobayashi, Eitaro Misawa, Naoko Takeuchi, Ken Univ Tokyo Dept Elect Engn & Informat Syst Bunkyo Tokyo 1138656 Japan

This work comprehensively analyzes the error robustness of hyperdimensional computing (HDC) by using FeFET-based local multiply and global accumulate computation-in-memory. HDC trains and infers with hypervectors (HVs). Symmetric or asymmetric errors, which simulate read-disturb and data-retention errors of FeFET, are injected into Item memory and/or Associative memory before/after or during training in various cases when solving European language classification task. The detailed error injection reveals that HDC is acceptable for both symmetric and asymmetric error rate up to 10(-1). Based on the detailed analysis of error robustness, training window slide (TWS) improves the error robustness against memory errors by removing data which contain different amount of errors. TWS shows 10 times higher error robustness. In addition, parallelization of HV encoding in training achieves fast training with up to 10 000 parallelism while maintaining the inference accuracy.

关键词： hyperdimensional computing FeFET computation-in-memory error robustness

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Simulated Annealing Algorithm & ReRAM Device Co-optimization for computation-in-memory

Simulated Annealing Algorithm & ReRAM Device Co-optimization...

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IEEE International memory Workshop (IMW)

作者： Taoka, Kenta Misawa, Naoko Koshino, Shunsuke Matsui, Chihiro Takeuchi, Ken Univ Tokyo Dept Elect Engn & Informat Syst Tokyo Japan

ISBN: (纸本)9781728185170

This paper co-optimizes simulated annealing (SA) algorithm and 40 nm TaOx-based resistive random access memory (ReRAM) for computation-in-memory (CiM) to solve combinatorial optimization problems such as the knapsack problem. SA in ReRAM CiM promises low power consumption, high throughput, and high scalability. However, in ReRAM, biterror occurs and 'Current window' becomes small. First, to overcome ReRAM device problems under high stress condition, Adaptive Endurance Relaxation (AER) is proposed to adaptively change the interval of relaxation based on Set/Reset cycles. By applying AER to ReRAM, Bit-Error Rate (BER) decreases by 100% and the current window increases by 21.2%. Second, SA algorithm mapping to ReRAM-based CiM is proposed. SA algorithm mapping enables ReRAM CiM to calculate Hamiltonian, which is equivalent to Ising model. By combining two proposals, SA Algorithm and Device Cooptimization (ADCO) improves the acceptable bit precision by 2 bits and the acceptable BER twice.

关键词： ReRAM simulated annealing computation-in-memory Ising model relaxation

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Event data-based computation-in-memory (CiM) configuration by co-designing integrated in-sensor and CiM computing for extremely energy-efficient edge computing

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JAPANESE JOURNAL OF APPLIED PHYSICS 2022年第SC期61卷 SC1085-SC1085页

作者： Matsui, Chihiro Higuchi, Kazuhide Koshino, Shunsuke Takeuchi, Ken Univ Tokyo Grad Sch Engn Dept Elect Engn & Informat Syst Tokyo 1138656 Japan

This paper discusses co-designing integrated in-sensor and in-memory computing based on the analysis of event data and gives a system-level solution. By integrating an event-based vision sensor (EVS) as a sensor and event-driven computation-in-memory (CiM) as a processor, event data taken by EVS are processed in CiM. In this work, EVS is used to acquire the scenery from a driving car and the event data are analyzed. Based on the EVS data characteristics of temporally dense and spatially sparse, event-driven SRAM-CiM is proposed for extremely energy-efficient edge computing. In the event-driven SRAM-CiM, a set of 8T-SRAMs stores multiple-bit synaptic weights of spiking neural networks. Multiply-accumulate operation with the multiple-bit synaptic weights is demonstrated by pulse amplitude modulation and pulse width modulation. By considering future EVS of high image resolution and high time resolution, the configuration of event-driven CiM for EVS is discussed.

关键词： computation-in-memory event-based vision sensor in-sensor computing SRAM

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