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97.6% array area reduction, ReRAM computation-in-memory with hyperparameter optimization based on memory bit-error rate and bit precision of log-encoding simulated annealing

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JAPANESE JOURNAL OF APPLIED PHYSICS 2022年第SC期61卷 SC1001-SC1001页

作者： Misawa, Naoko Taoka, Kenta Matsui, Chihiro Takeuchi, Ken Univ Tokyo Dept Elect Engn & Informat Syst Bunkyo Ku Tokyo 1138656 Japan

This paper proposes small array area and memory error tolerant resistive random access memory (ReRAM) computation-in-memory (CiM) with hyperparameter optimization based on bit-error rate (BER) and bit precision of log-encoding simulated annealing (SA). For combinatorial optimization problems, the proposed ReRAM CiM with log-encoding SA reduces the array area by 97.6%, compared with the conventional linear-encoding. To analyze ReRAM device error characteristics, "0" and "1" error injection is applied. The asymmetric ReRAM error improves the acceptable BER by 10 times and the acceptable bit precision to 4 bit. By adjusting the random flips and a cooling parameter, the numbers of flips and iterations decrease by 40% and 33%, respectively. Error injected (EI) iteration is changed to reproduce bit-error due to read disturb. The delay of EI iteration increases the acceptable BER by 25%. Furthermore, in the case of requiring extremely high accuracy, hyperparameter optimization improves the probability of obtaining the optimal answer by 1%.

关键词： ReRAM computation-in-memory simulated annealing combinatorial optimization problems

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NS-CIM: A Current-Mode computation-in-memory Architecture Enabling Near-Sensor Processing for Intelligent IoT Vision Nodes

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2020年第9期67卷 2909-2922页

作者： Liu, Zheyu Ren, Erxiang Qiao, Fei Wei, Qi Liu, Xinjun Luo, Li Zhao, Huichan Yang, Huazhong Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Tsinghua Univ BNRist Beijing 100084 Peoples R China Beijing Jiaotong Univ Sch Elect & Informat Engn Beijing 100044 Peoples R China Tsinghua Univ Dept Precis Instrument Beijing 100084 Peoples R China Tsinghua Univ Dept Mech Engn Beijing 100084 Peoples R China

In recent years, Neural networks (NNs) present vast potential for innovative applications. However, energy efficiency continues to remain a challenge in deploying NNs on the edge. In this context, computation-in-memory (CIM) architecture becomes an emerging trend in the area of energy-efficient hardware design, because it reduces data movement of multiply-accumulate (MAC) computation significantly. However, many recent works employ massive data converters to feed input data and transform output results, which may counteract the benefits of in-memory processing. To tackle this limitation, we propose a combined architecture cooperating sensor with CIM macro to achieve local processing of sensory signals. Current-mode computing techniques are exploited to achieve high energy efficiency while eliminating data conversion overhead. Moreover, we thoroughly analyze the non-idealities of the proposed mixed-signal circuits and present a co-design scheme to mitigate these imperfections. We have fabricated a 2-Kbit CIM macro in the proposed architecture with TSMC 65-nm technology. The fabricated chip achieved 60.6 TOPS/W energy efficiency while consuming 845.5 mu W power and 0.3 mm(2) core area, presenting a promising solution for energy-constrained edge devices.

关键词： computation-in-memory near-sensor processing Internet-of-Things binary-weight network always-on sensor

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computation-in-memory Based On Memristive Devices

Computation-In-Memory Based On Memristive Devices

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作者： H. A. Du Nguyen Delft University of Technology

学位级别：博士

In-memory computing is a promising computing paradigm due to its capability to alleviate the memory bottleneck. It has even higher potential when implemented usingmemristive devices ormemristors with various beneficial characteristics such as nonvolatility, high scalability, near-zero standby power consumption, high density, and CMOS compatibility. Exploring in-memory computing architectures in the combination withmemristor technology is still in its infancy phase. Therefore, it faces challenges with respect to the development of the devices, circuits, architectures, compilers and applications. This thesis focuses on exploring and developing in-memory computing in terms of architectures (including classification, limited schemes of instruction set, micro-architecture, communication and controller, as well as automation and simulator), and circuits (including logic synthesis flow and interconnect network schemes). In-memory architecture classification and survey - We first investigate the state-of-the- art of in-memory computing and propose a classification to have an overview on both existing and unexplored architectures. The classification is based on three main criteria: computation location (i. e., where the results are produced), memory technology (i. e., the memory technology is used), and computation parallelism (i. e., the maximum paral- lelism level can be exploited). Based on the computation, four main classes are derived: computation-inside-memory Array (CIM-A) which produces results inside the mem- ory and within the memory array, computation-in-memory Peripheral (CIM-P) which produces results inside the memory and within the peripheries, computation-outside- memory Near (COM-N) which produces results outside the memory and near the mem- ory core, and computation-outside-memory Far (COM-F) which which produces results outside the memory and far from the memory core, respectively. Subsequently, we re- view and compare the four classes and existing architec

关键词： Computer architecture Resistive computing computation-in-memory

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SySCIM: SystemC-AMS Simulation of Memristive computation In-memory

SySCIM: SystemC-AMS Simulation of Memristive Computation In-...

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25th Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Shadmehri, Seyed Hossein Hashemi BanaGozar, Ali Kamal, Mehdi Stuijk, Sander Afzali-Kusha, Ali Pedram, Massoud Corporaal, Henk Univ Tehran Sch Elect & Comp Engn Tehran Iran Eindhoven Univ Technol Elect Syst Grp Eindhoven Netherlands Univ Southern Calif Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9783981926361

computation-in-memory (CIM) is one of the most appealing computing paradigms, especially for implementing artificial neural networks. Non-volatile memories like ReRAMs, PCMs, etc., have proven to be promising candidates for the realization of CIM processors. However, these devices and their driving circuits are subject to non-idealities. This paper presents a comprehensive platform, named SysCIM, for simulating memristor-based CIM systems. SySCIM considers the impact of the non-idealities of the CIM components, including memristor device, memristor crossbar (interconnects), analog-to-digital converter, and transimpedance amplifier, on the vector-matrix multiplication performed by the CIM unit. The CIM modules are described in SystemC and SystemC-AMS to reach a higher simulation speed while maintaining high simulation accuracy. Experiments under different crossbar sizes show SySCIM performs simulations up to 117x faster than HSPICE with less than 4% accuracy loss. The modular design of SySCIM provides researchers with an easy design-space exploration tool to investigate the effects of various non-idealities.

关键词： simulation computation-in-memory memristor reliability

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A computation-in-memory Accelerator Based on Resistive Devices 19

A Computation-In-Memory Accelerator Based on Resistive Devic...

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International Symposium on memory Systems (MEMSYS)

作者： Hoang Anh Du Nguyen Yu, Jintao Abu Lebdeh, Muath Taouil, Mottaqiallah Hamdioui, Said Delft Univ Technol Delft Netherlands

ISBN: (纸本)9781450372060

Today's computing architectures suffer from the three well-known bottlenecks, which are the memory, the power and the instruction-level parallelism walls. Emerging non-volatile technologies, such as memristor, enable new resistive architectures that alleviate at least two of such bottlenecks, as they can process data within the memory with almost no leakage. In this paper, we propose a novel resistive computing architecture by extending a conventional architecture with a resistive based computation-in-memory accelerator (CIMX). We evaluate the delay, energy and area of the conventional and CIMX architecture using an analytical model and a simulation framework. The results (both based on the analytical model and simulation framework) show that the proposed architecture achieves at least one order of magnitude improvement in terms of performance, area, and energy efficiency for the considered benchmarks.

关键词： computation-in-memory Accelerator Resistive Computing Memristor

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SySCIM: SystemC-AMS simulation of memristive computation in-memory 22

SySCIM: SystemC-AMS simulation of memristive computation in-...

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Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe

作者： Seyed Hossein Hashemi Shadmehri Ali BanaGozar Mehdi Kamal Sander Stuijk Ali Afzali-Kusha Massoud Pedram Henk Corporaal University of Tehran Eindhoven University of Technology University of Southern California

ISBN: (纸本)9783981926361

Computation-in-memory (CIM) is one of the most appealing computing paradigms, especially for implementing artificial neural networks. Non-volatile memories like ReRAMs, PCMs, etc., have proven to be promising candidates for the realization of CIM processors. However, these devices and their driving circuits are subject to non-idealities. This paper presents a comprehensive platform, named SysCIM, for simulating memristor-based CIM systems. SySCIM considers the impact of the non-idealities of the CIM components, including memristor device, memristor crossbar (interconnects), analog-to-digital converter, and transimpedance amplifier, on the vector-matrix multiplication performed by the CIM unit. The CIM modules are described in SystemC and SystemC-AMS to reach a higher simulation speed while maintaining high simulation accuracy. Experiments under different crossbar sizes show SySCIM performs simulations up to 117× faster than HSPICE with less than 4% accuracy loss. The modular design of SySCIM provides researchers with an easy design-space exploration tool to investigate the effects of various non-idealities.

关键词： memristor simulation computation-in-memory

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A Domain-Specific Language and Compiler for computation-in-memory Skeletons 17

A Domain-Specific Language and Compiler for Computation-in-M...

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Great Lakes Symposium on VLSI (GLSVLSI)

作者： Yu, Jintao Hogervorst, Tom Nane, Razvan Delft Univ Technol Mekelweg 4 NL-2628 CD Delft Netherlands

ISBN: (纸本)9781450349727

computation-in-memory (CiM) is a new computer architecture template based on the in-memory computing paradigm. CiM can solve the memory-wall problem of classical Von Neumann-based computer systems by exploiting application-specific computational and data-flow patterns with the capability of performing both storage and computations of emerging resistive RAM technologies (e.g., memristors). However, to efficiently explore and design such radically new application-specific CiM architectures, we require fundamentally new algorithm specification and compilation techniques. In this paper, we introduce a domain-specific language to express not only the computational patterns of an algorithm but also its spatial characteristics. Furthermore, we design a compiler that is able to transform these patterns into highly-optimized CiM designs. Experiments demonstrate the functional correctness of the language and the compiler as well as an order of magnitude speedup improvement over a multicore system in both performance and energy costs.

关键词： Domain specific language computation-in-memory algorithmic skeleton memristor

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Challenges and Trends of Nonvolatile In-memory-computation Circuits for AI Edge Devices

IEEE OPEN JOURNAL OF THE SOLID-STATE CIRCUITS SOCIETY

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IEEE OPEN JOURNAL OF THE SOLID-STATE CIRCUITS SOCIETY 2021年 1卷 171-183页

作者： Hung, Je-Min Jhang, Chuan-Jia Wu, Ping-Chun Chiu, Yen-Cheng Chang, Meng-Fan Natl Tsing Hua Univ Inst Elect Engn Hsinchu 300 Taiwan

Nonvolatile memory (NVM)-based computing-in-memory (nvCIM) is a promising candidate for artificial intelligence (AI) edge devices to overcome the latency and energy consumption imposed by the movement of data between memory and processors under the von Neumann architecture. This paper explores the background and basic approaches to nvCIM implementation, including input methodologies, weight formation and placement, and readout and quantization methods. This paper outlines the major challenges in the further development of nvCIM macros and reviews trends in recent silicon-verified devices.

关键词： Artificial intelligence nonvolatile-memory NVM computation-in-memory CIM nvCIM

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RGB-Event Multi-Modal NV-CiM to Detect Object by Mapping-Oriented Enhanced-Feature Pyramid Network with Mapping-Aware Group Convolution

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2025年第3期E108A卷 482-490页

作者： Ichikawa, Yuya Misawa, Naoko Matsui, Chihiro Takeuchi, Ken Univ Tokyo Dept Elect Engn & Informat Syst Tokyo 1138656 Japan

To overcome the excessive memory capacity of nonvolatile CiM (NV-CiM) for multi-modal AI, this paper proposes Mapping- oriented enhanced-FPN (Feature Pyramid Network) fusion (More-FPN) as an RGB-event fusion object detection model. More-FPN includes three proposals. First proposal, Mapping-aware Group Convolution (MAGC), reduces the required NV-CiM capacity by suppressing the number of subarrays in NV-CiM at a fixed subarray size. In MAGC, the number of groups is optimized with no inference accuracy degradation. By adopting MAGC to FPN fusion of an RGB-event fusion object detection model, 54.7% subarrays are reduced. The second proposal, Separable Bridge (SepBridge), further reduces the number of subarrays by 26.1% from MAGC-adopted FPN fusion. Third proposal, Top-down path trainable BiFPN (TDT-BiFPN), achieves accuracy improvement with a slight subarray increase by adding bottom-up path and making top-down path trainable. By combining three proposals, More-FPN achieves both the reduction in subarrays by 61% and the accuracy improvement by 4.6%, compared with conventional FPN fusion CiM.

关键词： group convolution subarray separation multi-modal AI non-volatile memory computation-in-memory

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Co-design of SLC/MLC FeFET-based highly error-tolerant low-power CiM and strong lottery ticket hypothesis-based algorithm

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JAPANESE JOURNAL OF APPLIED PHYSICS 2024年第4期63卷 04SP06-04SP06页

作者： Yamauchi, Kenshin Yamada, Ayumu Misawa, Naoko Cho, Seong-Kun Toprasertpong, Kasidit Takagi, Shinichi Matsui, Chihiro Takeuchi, Ken Univ Tokyo Dept Elect Engn & Informat Syst Bunkyo Tokyo 1234567 Japan

This study co-designs single-level cell (SLC) mask and multilevel cell (MLC) weight twin FeFET devices and a strong lottery ticket hypothesis (SLTH)-based neural network (NN) algorithm to achieve highly error-tolerant low-power computation-in-memory (CiM). The SLC mask FeFET masks or transfers the NN weight stored in the MLC weight FeFET, and the masked NN weight reduces the CiM power consumption. The proposed SLC mask FeFETs, which are trained, and MLC weight FeFETs, in which V TH are uniformly randomized, achieve 87% inference accuracy against 10-year data retention and read disturb. The SLC mask FeFETs show 86% inference accuracy even at 2000 endurance cycles. In addition, shared-bottom-select-gate (BSG) SLTH CiM and common-mask SLTH CiM for the NN convolutional layer are proposed to reduce the CiM area by sharing BSG and mask FeFET. Moreover, NN weight mapping schemes for SLTH CiM are proposed. The proposed mapping schemes show a tradeoff between inference accuracy and CiM area. One of the schemes reduces the CiM area by 45% with a 9.1% accuracy loss.

关键词： computation-in-memory Strong Lottery Ticket Hypothesis FeFET

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