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REM-CiM: Attentional RGB-Event Fusion Multi-Modal Analog CiM for Area/Energy-Efficient Edge Object Detection during Both Day and Night

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IEICE TRANSACTIONS ON ELECTRONICS 2024年第10期E107C卷 426-435页

作者： Ichikawa, Yuya Yamada, Ayumu Misawa, Naoko Matsui, Chihiro Takeuchi, Ken Univ Tokyo Dept Elect Engn & Informat Syst Tokyo 1138656 Japan

Integrating RGB and event sensors improves object detection accuracy, especially during the night, due to the high-dynamic range of event camera. However, introducing an event sensor leads to an increase in computational resources, which makes the implementation of RGB-event fusion multi-modal AI to CiM difficult. To tackle this issue, this paper proposes RGB-Event fusion Multi-modal analog computation-in-memory (CiM), called REM-CiM, for multi-modal edge object detection AI. In REM-CiM, two proposals about multi-modal AI algorithms and circuit implementation are co-designed. First, memory capacity-Efficient Attentional Feature Pyramid Network (MEA-FPN), the model architecture for RGBevent fusion analog CiM, is proposed for parameter-efficient RGB-event fusion. Convolution-less bi-directional calibration (C-BDC) in MEA-FPN extracts important features of each modality with attention modules, while reducing the number of weight parameters by removing large convolutional operations from conventional BDC. Proposed MEA-FPN w/ C-BDC achieves a 76% reduction of parameters while maintaining mean Average Precision (mAP) degradation to < 2 . 3 % during both day and night, compared with Attentional FPN fusion (A-FPN), a conventional BDC-adopted FPN fusion. Second, the low-bit quantization with clipping (LQC) is proposed to reduce area/energy. Proposed REM-CiM with MEA-FPN and LQC achieves almost the same memory cells, 21% less ADC area, 24% less ADC energy and 0.17% higher mAP than conventional FPN fusion CiM without LQC.

关键词： computation-in-memory RGB-event fusion edge object detection multimodal AI event-based vision sensor event-based vision sensor

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Reliable and Energy-Efficient Diabetic Retinopathy Screening Using Memristor-Based Neural Networks

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IEEE ACCESS 2024年 12卷 47469-47482页

作者： Diware, Sumit Chilakala, Koteswararao Joshi, Rajiv V. Hamdioui, Said Bishnoi, Rajendra Delft Univ Technol Comp Engn Lab NL-2628 CD Delft Netherlands Capgemini Engn NL-5652 AA Eindhoven Netherlands IBM Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

Diabetic retinopathy (DR) is a leading cause of permanent vision loss worldwide. It refers to irreversible retinal damage caused due to elevated glucose levels and blood pressure. Regular screening for DR can facilitate its early detection and timely treatment. Neural network-based DR classifiers can be leveraged to achieve such screening in a convenient and automated manner. However, these classifiers suffer from reliability issue where they exhibit strong performance during development but degraded performance after deployment. Moreover, they do not provide supplementary information about the prediction outcome, which severely limits their widespread adoption. Furthermore, energy-efficient deployment of these classifiers on edge devices remains unaddressed, which is crucial to enhance their global accessibility. In this paper, we present a reliable and energy-efficient hardware for DR detection, suitable for deployment on edge devices. We first develop a DR classification model using custom training data that incorporates diverse image quality and image sources along with improved class balance. This enables our model to effectively handle both on-field variations in retinal images and minority DR classes, enhancing its post-deployment reliability. We then propose a pseudo-binary classification scheme to further improve the model performance and provide supplementary information about the model prediction. Additionally, we present an energy-efficient hardware design for our model using memristor-based computation-in-memory, to facilitate its deployment on edge devices. Our proposed approach achieves reliable DR classification with three orders of magnitude reduction in energy consumption over state-of-the-art hardware platforms.

关键词： Diabetic retinopathy neural networks computation-in-memory resistive random access memory RRAM memristor edge computing reliability

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Design-time Reference Current Generation for Robust Spintronic-based Neuromorphic Architecture

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ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS 2024年第1期20卷 1-20页

作者： Ahmed, Soyed Tuhin Mayahinia, Mahta Hefenbrock, Michael Muench, Christopher Tahoori, Mehdi B. Karlsruhe Inst Technol Chair Dependable Nano Comp Haid & Neu Str 7 D-76131 Karlsruhe Baden Wurttembe Germany Chair Pervas Comp Syst TECO Vincenz Priessnitz Str 1 D-76131 Karlsruhe Baden Wurttembe Germany

Neural Networks (NN) can be efficiently accelerated in a neuromorphic fabric based on emerging resistive non-volatile memories (NVM), such as Spin Transfer Torque MagneticRAM(STT-MRAM). Compared to other NVM technologies, STT-MRAM offers many benefits, such as fast switching, high endurance, and CMOS process compatibility. However, due to its low ON/OFF-ratio, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed current and, in turn, degradation of inference accuracy. In this article, we analyze the impact of the sensed accumulated current variation on the inference accuracy in Binary NNs and propose a design-time reference current generation method to improve the robustness of the implemented NN under different temperature and process variation scenarios (up to 125. C). Our proposed method is robust to both process and temperature variations. The proposed method improves the accuracy of NN inference by up to 20.51% on the MNIST, Fashion-MNIST, and CIFAR-10 benchmark datasets in the presence of process and temperature variations without additional runtime hardware overhead compared to existing solutions.

关键词： computation-in-memory STT-MRAM neuromorphic computing variations robust neural network acceleration

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Energy-efficient and fast memristor-based serial multipliers applicable in image processing

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RESULTS IN ENGINEERING 2025年 25卷

作者： Fatemieh, Seyed Erfan Bagheralmoosavi, Bahareh Reshadinezhad, Mohammad Reza Univ Isfahan Fac Comp Engn Dept Comp Architecture Esfahan *** Iran

computation-in-memory (CIM) is a promising technique for overcoming the Von-Neumann bottleneck. Applying memristors in CIM reduces data transfer between processor and memory. Memristive CIM reduces energy consumption and processing time of data-intensive applications. Multipliers are one of the arithmetic circuits that play a significant role in data-intensive processing applications. Serial Material Implication (IMPLY) logic design implements arithmetic circuits by applying emerging memristive technology that enables CIM Array (CIM-A). The computational complexity of IMPLY-based multipliers for use in the CIM-A architecture is a significant design challenge. Implementing IMPLY-based crossbar array-friendly multipliers and reducing their computational cycles and energy consumption are designers' goals in applying computational applications such as convolution in the basic CIM-A architecture. This work presents unsigned and signed array multipliers using serial IMPLY logic. The proposed multipliers have improved significantly compared to State-Of-the Art (SOA) by applying the proposed Partial Product Units (PPUs) and overlapping computational steps. The number of computational steps, energy consumption, and required memristors of the proposed 8-bit unsigned array multiplier are improved by up to 36 %, 31 %, and 47 % compared to the classic designs. The proposed 8-bit signed multiplier has also improved the computational steps, energy consumption, and required memristors by up to 59 %, 54 %, and 45 %. The performance of the proposed multipliers in the applications of Gaussian blur and edge detection is also investigated, and the simulation results have shown an improvement of 31 % in energy consumption and 33 % in the number of computational steps in these applications.

关键词： Memristor IMPLY logic Multiplier Image processing computation-in-memory Processing in-memory

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Design methodology of compact edge vision transformer CiM considering non-volatile memory bit precision and memory error tolerance

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JAPANESE JOURNAL OF APPLIED PHYSICS 2024年第3期63卷 03SP05-03SP05页

作者： Misawa, Naoko Yamaguchi, Ryuhei Yamada, Ayumu Wang, Tao Matsui, Chihiro Takeuchi, Ken Univ Tokyo Dept Elect Engn & Informat Syst Bunkyo Tokyo 1138656 Japan

This paper proposes a design methodology for a compact edge vision transformer (ViT) computation-in-memory (CiM). ViT has attracted much attention for its high inference accuracy. However, to achieve high inference accuracy, the conventional ViT requires fine-tuning many parameters with pre-trained models on large datasets and a large number of matrix multiplications in inference. Thus, to map ViT to non-volatile memory (NVM)-based CiM compactly for edge applications (IoT/Mobile devices) in inference, this paper analyses fine-tuning in training, clipping, and quantization in inference. The proposed compact edge ViT CiM can be optimized by three design methods according to use cases considering the required fine-tuning time, ease of setting memory bit precision, and memory error tolerance of ViT CiM. As a result, in CIFAR-10, the most compact type successfully reduces the total memory size of ViT by 85.8% compared with the conventional ViT. Furthermore, the high accuracy type and high error-tolerant type improve inference accuracy by 4.4% and memory-error tolerance by more than four times compared with convolutional neural networks, respectively. (c) 2024 The Japan Society of Applied Physics

关键词： vision transformer computation-in-memory non-volatile memory quantization aware training

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Accurate and Energy-Efficient Bit-Slicing for RRAM-Based Neural Networks

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IEEE TRANSACTIONS ON EMERGING TOPICS IN computationAL INTELLIGENCE 2023年第1期7卷 164-177页

作者： Diware, Sumit Singh, Abhairaj Gebregiorgis, Anteneh Joshi, Rajiv V. Hamdioui, Said Bishnoi, Rajendra Delft Univ Technol Dept Comp Engn NL-2628 CD Delft Netherlands IBM Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

computation-in-memory (CIM) paradigm leverages emerging memory technologies such as resistive random access memories (RRAMs) to process the data within the memory itself. This alleviates the memory-processor bottleneck resulting in much higher hardware efficiency compared to von-Neumann architecture-based conventional hardware. Hence, CIM becomes an attractive alternative for applications like neural networks which require a huge number of data transfer operations in conventional hardware. CIM-based neural networks typically employ bit-slicing scheme which represents a single neural weight using multiple RRAM devices (called slices) to meet the high bit-precision demand. However, such neural networks suffer from significant accuracy degradation due to non-zero G(min) error where a zero weight in the neural network is represented by an RRAM device with a non-zero conductance. This paper proposes an unbalanced bit-slicing scheme to mitigate the impact of non-zero G(min) error. It achieves this by allocating appropriate sensing margins for different slices based on their binary positions. It also tunes the sensing margins to meet the demands of either high accuracy or energy-efficiency. The sensing margin allocation is supported by 2's complement arithmetic which further reduces the influence of non-zero G(min) error. Simulation results show that our proposed scheme achieves up to 7.3x accuracy and up to 7.8x correct operations per unit energy consumption compared to state-of-the-art.

关键词： Neural networks Sensors Arithmetic Voltage Virtual machine monitors Degradation Common Information Model (computing) computation-in-memory bit-slicing neural networks non-zero G(min) error conductance variation non-idealities

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Efficient Signed Arithmetic Multiplication on Memristor-Based Crossbar

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IEEE ACCESS 2023年 11卷 33964-33978页

作者： Zahedi, Mahdi Shahroodi, Taha Wong, Stephan Hamdioui, Said Delft Univ Technol TU Delft EEMCS Fac QCE Dept NL-2628 CD Delft Netherlands

The vast potential of memristor-based computation-in-memory (CIM) engines has mainly triggered the mapping of best-suited applications. Nevertheless, with additional support, existing applications can also benefit from CIM. In particular, this paper proposes an energy and area-efficient CIM-based methodology to perform arithmetic signed matrix multiplications. Our approach combines a) the mapping of the signed operands on the 1T1R crossbar, and b) the augmentation of the periphery with customized circuits to support the execution of shift and accumulate needed for the arithmetic operations. The operand mapping is performed without the need for sign extension;hence, reducing the required memory size. To demonstrate the superiority of our scheme as compared with the state-of-the-art, simulations are performed for different case studies including a neural network and two kernels which are taken from the Polybench/C benchmark suite. The results show that our approach achieves up to 8x energy-saving and 3x area-saving compared with other CIM-based prior works.

关键词： Memristor computation-in-memory signed computation

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NeuroScrub plus : Mitigating Retention Faults Using Flexible Approximate Scrubbing in Neuromorphic Fabric Based on Resistive Memories

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2023年第5期42卷 1490-1503页

作者： Ahmed, Soyed Tuhin Hefenbrock, Michael Muench, Christopher Tahoori, Mehdi B. Karlsruhe Inst Technol Comp Sci Dept D-76131 Karlsruhe Germany

Neuromorphic computation-in-memory fabric based on emerging nonvolatile memories considered an attractive option to accelerate neural networks (NNs) in hardware as they provide high-performance, low-power, and reduced data movement. Although nonvolatile resistive memories (NVMs) offer many benefits, they are susceptible to data retention faults, where previously stored data are not retained after a certain amount of time due to external influence. These faults are more likely to happen unidirectional and severely impact the inference accuracy of the hardware implementation of NNs since the synaptic weights stored in the NVMs are subject to retention faults. In this work, we propose an approximate scrubbing technique for NVM-based neuromorphic fabric to mitigate unidirectional retention faults with virtually zero storage overhead depending on the definition of scrub area for multilayer perceptron (MLP) and convolutional NNs (CNNs). The training of the NNs is adjusted accordingly to meet the requirements of the proposed approximate scrubbing scheme. On different benchmarks, the proposed scrubbing approach can improve the inference accuracy up to 85.51% for MLP and 87.76% for CNN over the expected device operational time with negligible storage overhead.

关键词： computation-in-memory magnetic tunnel junction (MTJ) Neuromorphic computing neuromorphic nonvolatile memory (NVM) retention faults

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Severity-Based Hierarchical ECG Classification Using Neural Networks

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 2023年第1期17卷 77-91页

作者： Diware, Sumit Dash, Sudeshna Gebregiorgis, Anteneh Joshi, Rajiv V. V. Strydis, Christos Hamdioui, Said Bishnoi, Rajendra Delft Univ Technol Comp Engn Dept NL-2628 CD Delft Netherlands ASML Holding NV NL-5504 DR Veldhoven Netherlands IBM Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA Delft Univ Technol Erasmus Med Ctr NL-3015 CN Rotterdam Netherlands

Timely detection of cardiac arrhythmia characterized by abnormal heartbeats can help in the early diagnosis and treatment of cardiovascular diseases. Wearable healthcare devices typically use neural networks to provide the most convenient way of continuously monitoring heart activity for arrhythmia detection. However, it is challenging to achieve high accuracy and energy efficiency in these smart wearable healthcare devices. In this work, we provide architecture-level solutions to deploy neural networks for cardiac arrhythmia classification. We have created a hierarchical structure after analyzing various neural network topologies where only required network components are activated to improve energy efficiency while maintaining high accuracy. In our proposed architecture, we introduce a severity-based classification approach to directly help the users of the wearable healthcare device as well as the medical professionals. Additionally, we have employed computation-in-memory based hardware to improve energy efficiency and area consumption by leveraging in-situ data processing and scalability of emergingmemory technologies such as resistive random accessmemory (RRAM). Simulation experiments conducted using the MIT-BIH arrhythmia dataset show that the proposed architecture provides high accuracy while consuming average energy of 0.11 mu J per heartbeat classification and 0.11 mm2 area, thereby achieving 25x improvement in average energy consumption and 12x improvement in area compared to the stateof-the-art.

关键词： Arrhythmia computation-in-memory ECG neural networks resistive random access memory (RRAM) severity-based classification

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Bit slicing approaches for variability aware ReRAM CIM macros

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IT-INFORMATION TECHNOLOGY 2023年第1-2期65卷 3-12页

作者： Bengel, Christopher Dixius, Leon Waser, Rainer Wouters, Dirk J. Menzel, Stephan Forschungszentrum Julich Peter Grunberg Inst 7 D-52428 Julich Germany Rhein Westfal TH Aachen Inst Elect Mat 2 D-52074 Aachen Germany

computation-in-memory accelerators based on resistive switching devices represent a promising approach to realize future information processing systems. These architectures promise orders of magnitudes lower energy consumption for certain tasks, while also achieving higher throughputs than other special purpose hardware such as GPUs, due to their analog computation nature. Due to device variability issues, however, a single resistive switching cell usually does not achieve the resolution required for the considered applications. To overcome this challenge, many of the proposed architectures use an approach called bit slicing, where generally multiple low-resolution components are combined to realize higher resolution blocks. In this paper, we will present an analog accelerator architecture on the circuit level, which can be used to perform Vector-Matrix-Multiplications or Matrix-Matrix-Multiplications. The architecture consists of the 1T1R crossbar array, the optimized select circuitry and an ADC. The components are designed to handle the variability of the resistive switching cells, which is verified through our verified and physical compact model. We then use this architecture to compare different bit slicing approaches and discuss their tradeoffs.

关键词： bit slicing computation-in-memory memristive devices Vector-Matrix-Multiplications

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