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International memory Workshop (IMW)

作者： Kwon, Youngjae Koo, Won-Tae Park, Sangsu Suh, Dong Ik Lee, Gunhee Lee, Hyung Dong Ahn, Youngbae Kim, Dohee Ryu, Seungwook Em, Hoseok Kang, Seokjoon Jeong, Chang Won Cheon, Junho Choi, Hyejung Kim, Soo Gil Lee, Seho Yi, Jaeyun Cha, Seon Yong SK Hynix Inc Icheon Gyeonggi Do South Korea

ISBN: (纸本)9798350306521

Non-volatile memory-based analog computation-in-memory can improve energy efficiency and latency of artificial intelligence edge devices by minimizing the movement of data between processors and memories. Here, we developed reliable HfO2-based resistive synaptic cell (RSC) arrays with 16-level analog properties. We revealed that oxygen diffusion barriers not only suppress the negative-set phenomenon and but also improve retention properties. In addition, we fully integrated 256Kcell 1T1R cross-bar RSC arrays using a conventional CMOS process, and demonstrated their improved multiply-accumulate operations with similar to 94% accuracy.

关键词： analog computation-in-memory multiplication-and-accumulation resistive synaptic cell oxygen diffusion barrier

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A Survey on memory-centric Computer Architectures

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ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS 2022年第4期18卷 1–50页

作者： Gebregiorgis, Anteneh Hoang Anh Du Nguyen Yu, Jintao Bishnoi, Rajendra Taouil, Mottaqiallah Catthoor, Francky Hamdioui, Said Delft Univ Technol Mekelweg 4 NL-2628 CD Delft Netherlands Interuniv Microelect Ctr IMEC Leuven Belgium

Faster and cheaper computers have been constantly demanding technological and architectural improvements. However, current technology is suffering from three technology walls: leakage wall, reliability wall, and cost wall. Meanwhile, existing architecture performance is also saturating due to three well-known architecture walls: memory wall, power wall, and instruction-level parallelism (ILP) wall. Hence, a lot of novel technologies and architectures have been introduced and developed intensively. Our previous work has presented a comprehensive classification and broad overview of memory-centric computer architectures. In this article, we aim to discuss the most important classes of memory-centric architectures thoroughly and evaluate their advantages and disadvantages. Moreover, for each class, the article provides a comprehensive survey on memory-centric architectures available in the literature.

关键词： computation-in-memory computer architectures resistive computing classification

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Towards a Robust Multiply-Accumulate Cell in Photonics using Phase-Change Materials

Towards a Robust Multiply-Accumulate Cell in Photonics using...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Cardoso, Raphael Zrounba, Clement Abdalla, Mohab Jimenez, Paul de Queiroz, Mauricio Gomes Charbonnier, Benoit Pavanello, Fabio O'Connor, Ian Le Beux, Sebastien Univ Lyon CNRS Ecole Centrale Lyon INSA LyonCPE LyonINLUMR5270 Ecully France RMIT Univ Sch Engn Melbourne Vic 3000 Australia CEA LETI Grenoble Grenoble France Concordia Univ Dept Elect & Comp Engn Montreal PQ Canada

ISBN: (纸本)9798350396249

In this paper we propose a novel approach to multiply-accumulate (MAC) operations in photonics. This approach is based on stochastic computing and on the dynamic behavior of phase-change materials (PCMs), leading to the unique characteristic of automatically storing the result in nonvolatile memory. We demonstrate that, even with perfect look-up tables, the standard approach to PCM scalar multiplication is highly susceptible to perturbations as small as 0.1% of the input power, causing repetitive peaks of 600% relative error. In the same operating conditions, the proposed method achieves an average of 7x improvement in precision.

关键词： photonic computing phase-change memories stochastic computing computation-in-memory

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Lightspeed Binary Neural Networks using Optical Phase-Change Materials

Lightspeed Binary Neural Networks using Optical Phase-Change...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Shahroodi, Taha Cardoso, Raphael Zahedi, Mahdi Wong, Stephan Bosio, Alberto O'Connor, Ian Hamdioui, Said Delft Univ Technol Dept Quantum & Comp Engn Delft Netherlands Ecole Cent Lyon Inst Nanotechnol Lyon Lyon France

ISBN: (纸本)9798350396249

This paper investigates the potential of a compute-in-memory core based on optical Phase Change Materials (oPCMs) to speed up and reduce the energy consumption of the Matrix-Matrix-Multiplication operation. The paper also proposes a new data mapping for Binary Neural Networks (BNNs) tailored for our oPCM core. The preliminary results show a significant latency improvement irrespective of the evaluated network structure and size. The improvement varies from network to network and goes up to similar to 1053x.

关键词： Binary Neural Network Optical PCM computation-in-memory

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Lift: Exploiting Hybrid Stackedmemory for Energy-Efficient Processing of Graph Convolutional Networks 60

Lift: Exploiting Hybrid StackedMemory for Energy-Efficient P...

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60th ACM/IEEE Design Automation Conference (DAC)

作者： Chen, Jiaxian Zhong, Zhaoyu Sun, Kaoyi Ma, Chenlin Mao, Rui Wang, Yi Shenzhen Univ Coll Comp Sci & Software Engn Shenzhen Peoples R China

ISBN: (纸本)9798350323481

Graph Convolutional Networks (GCNs) are powerful learning approaches for graph-structured data. GCNs are both computing- and memory-intensive. The emerging 3D-stacked computation-in-memory (CIM) architecture provides a promising solution to process GCNs efficiently. The CIM architecture can provide near-data computing, thereby reducing data movement between computing logic and memory. However, previous works do not fully exploit the CIM architecture in both dataflow and mapping, leading to significant energy consumption. This paper presents Lift, an energy-efficient GCN accelerator based on 3D CIM architecture using software and hardware co-design. At the hardware level, Lift introduces a hybrid architecture to process vertices with different characteristics. Lift adopts near-bank processing units with a push-based dataflow to process vertices with strong re-usability. A dedicated unit is introduced to reduce massive data movement caused by high-degree vertices. At the software level, Lift adopts a hybrid mapping to further exploit data locality and fully utilize the hybrid computing resources. The experimental results show that the proposed scheme can significantly reduce data movement and energy consumption compared with representative schemes.

关键词： 3D-Stacked memory computation-in-memory Graph Convolutional Networks Accelerator

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CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out 4

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Char...

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IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) - Intelligent Technology in the Post-Pandemic Era

作者： Singh, Abhairaj Zahedi, Mahdi Shahroodi, Taha Gupta, Mohit Gebregiorgis, Anteneh Komalan, Manu Joshi, Rajiv, V Catthoor, Francky Bishnoi, Rajendra Hamdioui, Said Delft Univ Technol Comp Engn Lab Delft Netherlands IMEC Leuven Leuven Belgium IBM Thomas J Watson Res Ctr Yorktown Hts NY USA

ISBN: (数字)9781665409964

ISBN: (纸本)9781665409964

Spin-transfer torque magnetic random access memory (STT-MRAM) based computation-in-memory (CIM) architectures have shown great prospects for an energy-efficient computing. However, device variations and non-idealities narrow down the sensing margin that severely impacts the computing accuracy. In this work, we propose an adaptive referencing mechanism to improve the sensing margin of a CIM architecture for boolean binary logic (BBL) operations. We generate reference signals using multiple STT-MRAM devices and place them strategically into the array such that these signals can address the variations and trace the wire parasitics effectively. We have demonstrated this behavior using an STT-MRAM model, which is calibrated using 1Mbit characterized array. Results show that our proposed architecture for binary neural networks (BNN) achieves up to 17.8 TOPS/W on the MNIST dataset and 130x performance improvement for the text encryption compared to the software implementation on Intel Haswell processor.

关键词： STT-MRAM computation-in-memory binary logic binary neural networks

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A failure analysis framework of ReRAM In-memory Logic operations 6

A failure analysis framework of ReRAM In-Memory Logic operat...

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6th IEEE International Test Conference in Asia (ITC-Asia)

作者： Brackmann, L. Jafari, A. Bengel, C. Mayahinia, M. Waser, R. Wouters, D. Menzel, S. Tahoori, M. Inst Werkstoffe Elektrotech II RWTH Aachen Aachen Germany KIT Dept Comp Sci Karlsruhe Germany Forschungszentrum Julich Peter Grunberg Inst PGI 7 Julich Germany Forschungszentrum Julich Peter Grunberg Inst PGI 10 Julich Germany

ISBN: (数字)9781665455237

ISBN: (纸本)9781665455237

computation-in-memory (CiM) with emerging nonvolatile memories leads to significant performance and energy emclency, whieh Is a promising approaeh to address so-called memorywallofconventional von Neumann architectures. Redoxbased Random. access memory (ReRAM) is an appropriate candidate for the realization of CiM coneepls in CMOS cointegrated crossbar structures. However, ReRAMdevices sufl'er from. inherent variability in fabrication and operation. In this paper, we propose a sta1istical failure probability framework for the reliability evaluation of ReRAM-based CiM. Based on thls, a comprebensive reliability anaIysi is Is performed for logic operations in ReRAM-based Scouting and MAGIC concepts at the crossbar level. Our proposed framework shows that existing logic operation in the crossbar architecture bas a high failnre probability due to the variability and crossbar non-idealities. Hence, a modified crossbar design is proposed to achieve the target reliability requirements.

关键词： computation-in-memory Memristor-aided Logic (MAGIC) Sconting Logic Redox-based Random access memory (ReRAM) Variability

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Edge Retraining of FeFET LM-GA CiM for Write Variation & Reliability Error Compensation

Edge Retraining of FeFET LM-GA CiM for Write Variation & Rel...

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14th IEEE International memory Workshop (IMW)

作者： Yoshikiyo, Shinsei Misawa, Naoko Toprasertpong, Kasidit Takagi, Shinichi Matsui, Chihiro Takeuchi, Ken Univ Tokyo Dept Elect Engn & Informat Syst Tokyo Japan

ISBN: (纸本)9781665499477

This paper proposes an edge retraining method for local multiply and global accumulate (LM-GA) FeFET computation-in-memory (CiM) to compensate the accuracy degradation of neural network (NN) by FeFET device errors. The weights of the original NN model, accurately trained in cloud data center, are written into edge FeFET LM-GA CiM and changed by FeFET device errors in the field. By partially retraining the NN model at the edge device, the effect of device errors is reduced. The proposed method can retrain with small data according to the capacity of the edge device. Three types of FeFET errors, write variation, read disturbance, and data retention, are modeled based on actual device measurements for evaluation. From the evaluation, for the three types of FeFET errors, more than 50% of the reduced inference accuracy can be recovered. Furthermore, by adding a few more layers of retraining, the accuracy recovery rate increased by 20-30%. When the data used for retraining are reduced to 1%, the accuracy recovery rate decreases by about only 15%.

关键词： computation-in-memory FeFET error compensation write variation read-disturb data-retention

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Versatile FeFET Voltage-sensing Analog CiM for Fast & Small- area Hyperdimensional Computing

Versatile FeFET Voltage-sensing Analog CiM for Fast & Small-...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Matsui, Chihiro Kobayashi, Eitaro Toprasertpong, Kasidit Takagi, Shinichi Takeuchi, Ken Univ Tokyo Dept Elect Engn & Informat Syst Tokyo Japan

ISBN: (纸本)9781665484855

This paper proposes fast and small-area FeFETbased voltage-sensing analog computation-in-memory (CiM) for hyperdimensional computing (HDC) by eliminating largescale digital circuit overhead. In both training and inference of HDC, MAP (bit-wise XOR, bit-wise majority rule, and 1bit shift) of hypervectors (HVs) is operated by Partially added Text HV FeFET CiM and Text HV FeFET. In inference, Similarity search FeFET CiM obtains classification result. By taking an example of Language classification problem, the proposed voltage-sensing FeFET CiM for HDC encodes HV in training phase by 5,000 times faster and smaller area than the conventional method.

关键词： FeFET hyperdimensional computing computation-in-memory hypervector language classification

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Hamming Distance computation in Unreliable Resistive memory

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IEEE TRANSACTIONS ON COMMUNICATIONS 2018年第11期66卷 5013-5027页

作者： Chen, Zehui Schoeny, Clayton Dolecek, Lara Univ Calif Los Angeles Elect & Comp Engn Dept Los Angeles CA 90095 USA

Enabled by new storage mediums, computation-inmemory is a novel architecture that has shown great potential in reducing the burden of massive data processing by bypassing the communication and memory access bottleneck. Suggested by Cassuto and Crammer, allowing for ultra-fast Hamming distance computations to be performed in resistive memory with low-level conductance measurements has the potential to drastically speed up many modern machine learning algorithms. Meanwhile, Hamming distance computation-in-memory remains a challenging task as a result of the non-negligible device variability in practical resistive memory. In this paper, build upon the work of Cassuto and Crammer, we study memristor variability due to two distinct sources: resistance variation, and the non-deterministic write process. First, we introduce a technique for estimating the Hamming distance under resistance variation alone. Then, we propose error-detection and error-correction schemes to deal with non-ideal write process. We then combine these results to concurrently address both sources of memristor variabilities. In order to preserve the low latency property of computation-inmemory, all of our approaches rely on only a single vector-level conductance measurement. We use so-called inversion coding as a key ingredient in our solutions and we prove the optimality of this code given the restrictions on bit-accessible information. Finally, we demonstrate the efficacy of our approaches on the k-nearest neighbors classifier.

关键词： computation-in-memory error detection and correction resistive RAM k-nearest neighbors classification Hamming distance

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