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SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for Memristor-Based CIM Architectures

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2021年第5期68卷 1917-1930页

作者： Singh, Abhairaj Abu Lebdeh, Muath Gebregiorgis, Anteneh Bishnoi, Rajendra Joshi, Rajiv, V Hamdioui, Said Delft Univ Technol Comp Engn Dept NL-2628 CD Delft Netherlands IBM Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

Emerging computation-in-memory (CIM) paradigm offers processing and storage of data at the same physical location, thus alleviating critical memory-processor communication bottlenecks suffered by conventional von-Neumann architecture. Storage of data in a CIM architecture is analog in nature and therefore computation is performed in analog domain i.e. inputs and outputs are analog values. Since the outside computing environment is digital, analog-to-digital converters (ADC) are utilized to perform the output data conversion. However, ADC designs are bulky, power-hungry circuits that are prone to design variations and therefore, play an important role in determining the computing efficiency of CIM architectures. In this paper, we present a scalable and reliable integrate and fire circuit ADC (SRIF-ADC) design for CIM architectures, suitable for stringent power and area constraints. We devise a technique to stabilize the node receiving analog inputs that allows more rows to be activated at the same time, thereby increasing the operand size of input vectors. This allows better scalability in terms of higher parallelism of operations. We employ a self-timed variation-aware design approach and design measures to drastically reduce read disturb of memristor devices that address reliability issues related to the ADC design. In addition, we present a compact, built-in sample-and-hold circuit to replace the large-sized capacitance and built-in weighting technique to alleviate the need for post-processing. For multiply-and-accumulate (MAC) operation, our simulation results show that we can improve the computational parallelism by 3X as well as ADC conversion speed and energy efficiency are improved by 2X and 11.6X, respectively, compared to the state-of-the-art design.

关键词： Computer architecture Common Information Model (computing) Memristors Resistance Reliability Performance evaluation Switches Memristor computation-in-memory analog-to-digital converters adder multiply-and-accumulate integrate and fire circuit

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A Classification of memory-Centric Computing

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ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS 2020年第2期16卷 1–26页

作者： Hoang Anh Du Nguyen Yu, Jintao Abu Lebdeh, Muath Taouil, Mottaqiallah Hamdioui, Said Catthoor, Francky Delft Univ Technol Mekelweg 4 NL-2628 CD Delft Netherlands Interuniv Microelect Ctr IMEC Leuven Belgium

Technological and architectural improvements have been constantly required to sustain the demand of faster and cheaper computers. However, CMOS down-scaling is suffering from three technology walls: leakage wall, reliability wall, and cost wall. On top of that, a performance increase due to architectural improvements is also gradually saturating due to three well-known architecture walls: memory wall, power wall, and instruction-level parallelism (ILP) wall. Hence, a lot of research is focusing on proposing and developing new technologies and architectures. In this article, we present a comprehensive classification of memory-centric computing architectures;it is based on three metrics: computation location, level of parallelism, and used memory technology. The classification not only provides an overview of existing architectures with their pros and cons but also unifies the terminology that uniquely identifies these architectures and highlights the potential future architectures that can be further explored. Hence, it sets up a direction for future research in the field.

关键词： computation-in-memory resistive computing memory-centric computer architectures

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Ternary Łukasiewicz logic using memristive devices

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Neuromorphic Computing and Engineering 2023年第4期3卷 044001-044001页

作者： Bengel, Christopher Liu, Feng Chen, Ziang Zhao, Xianyue Waser, Rainer Schmidt, Heidemarie Du, Nan Menzel, Stephan Institute for Electronic Materials 2 RWTH Aachen University Aachen Germany Peter Grünberg Institut 7 Forschungszentrum Jülich Jülich Germany Peter Grünberg Institut 10 Forschungszentrum Jülich Jülich Germany Institute for Solid State Physics Friedrich Schiller University Jena Jena Germany Department of Quantum Detection Leibniz Institute of Photonic Technology (IPHT) Jena Germany

Memristive devices based on the Valence Change Mechanism (VCM) are promising devices for storage class memory, neuromorphic computing and logic-in-memory (LIM) applications. They are suited for such a wide range of applications, due to their possibility for extreme dense integration, low power consumption and multilevel capabilities. Through LIM concepts, Boolean logic operations can be performed directly in memory. In many of these concepts, the resistance state of the device is interpreted as the logical input and output of the logic function, which is why these concepts are called ‘stateful’ logic. Most of the proposed ideas, however, are defined based on only binary switching VCM devices and neglect their multi-level capabilities. Extending LIM concepts towards multinary logic, e.g. a ternary logic, would increase the data density inside the memory array and reduce the number of devices required to perform a certain operation. In this work, we discuss two possibilities of realizing a ternary logic based on the analog switching in the RESET or in the SET direction. For both directions we verify the logic functionality by showing the basic operations of implication, negation and false operation, which together form a functionally complete logic. Additionally, for both switching directions, we discuss a 41-Trit ( ≈ 64-Bit) addition. For all investigations the physics-based compact model JART VCM v1b is used, which has been verified on the RESET direction multilevel properties of the TaO x devices. © 2023 The Author(s). Published by IOP Publishing Ltd

关键词： adder computation-in-memory logic memristive devices VCM

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Versatile FeFET Voltage-sensing Analog CiM for Fast & Small-area Hyperdimensional Computing

Versatile FeFET Voltage-sensing Analog CiM for Fast & Small-...

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IEEE International Symposium on Circuits and Systems

作者： Chihiro Matsui Eitaro Kobayashi Kasidit Toprasertpong Shinichi Takagi Ken Takeuchi De. of Eecric Engineering nd Inforion Syses The Universiy of Tokyo JnDe. of Eecric Engineering nd Inforion Syses The Universiy of Tokyo JnDe. of Eecric Engineering nd Inforion Syses The Universiy of Tokyo JnDe. of Eecric Engineering nd Inforion Syses The Universiy of Tokyo JnDe. of Eecric Engineering nd Inforion Syses The Universiy of Tokyo Jn

ISBN: (数字)9781665484855

ISBN: (纸本)9781665484862

This paper proposes fast and small-area FeFET-based voltage-sensing analog computation-in-memory (CiM) for hyperdimensional computing (HDC) by eliminating large-scale digital circuit overhead. In both training and inference of HDC, MAP (bit-wise XOR, bit-wise majority rule, and 1-bit shift) of hypervectors (HVs) is operated by Partially added Text HV FeFET CiM and Text HV FeFET. In inference, Similarity search FeFET CiM obtains classification result. By taking an example of Language classification problem, the proposed voltage-sensing FeFET CiM for HDC encodes HV in training phase by 5,000 times faster and smaller area than the conventional method.

关键词： FeFET hyperdimensional computing computation-in-memory hypervector language classification

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Energy Efficient 9T SRAM With R/W Margin Enhanced for beyond Von-Neumann computation 24

Energy Efficient 9T SRAM With R/W Margin Enhanced for beyond...

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24th International Symposium on VLSI Design and Test (VDAT)

作者： Rajput, Anil Kumar Pattanaik, Manisha ABV IIITM VLSI Design Lab Gwalior Madhya Pradesh India

ISBN: (纸本)9781728193694

The state-of-the-art computing systems based on traditional von-Neumann architectures are facing von-Neumann bottlenecks(VNB), which has large impact on computing speed and energy consumption of current computing system for big-data applications. computation-in-memory (CIM) architecture is prominent candidate for computation to break VNB. In this paper, we propose a 9T (P9T) SRAM bit-cell that is energy efficient and at the same time, it enhances the read/write margin. The simulation result shows that the P9T SRAM design increases Read SNM (RSNM), Write SNM (WSNM), Dynamic noise margin (DNM) and I-on/I-off by 25.44%, 19.44%, 56.41% and 102.5%, respectively at 1.8V supply voltage over Conventional 8T (C8T) SRAM cell in a 180nm CMOS technology. The P9T SRAM design decrease read and write energy per operation by 60.85% and 22.67%, respectively over the C8T SRAM bit-cell. Finally for illustration of beyond von-Neumann computation, the In-memory Boolean computation (IMBC) operation has been demonstrated using P9T SRAM cell, wbieb shows energy efficieney improvement of 28% over IMBC operation in C8T SRAM bit-cell.

关键词： computation-in-memory Energy-efficient SRAM Von-Neumann bottlenecks

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From emerging memory to novel devices for neuromorphic systems: consequences for the reliability requirements of memristive devices

From emerging memory to novel devices for neuromorphic syste...

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IEEE International Reliability Physics Symposium (IRPS)

作者： Wouters, D. J. Rhein Westfal TH Aachen Inst Elect Mat IWE 2 Sommerfeldstr 24 D-52074 Aachen Germany Rhein Westfal TH Aachen JARA FIT Sommerfeldstr 24 D-52074 Aachen Germany

ISBN: (纸本)9781538695043

Memristive devices have been developed initially for memories, where they function as a non-volatile memory element. While the different kinds of memristive devices have their own operational as well as reliability concerns, the specifications are clearly set by the memory application (e. g., embedded, standalone, or storage-class type). More recently, memristive devices became of high interest for enabling new hardware concepts for a variety of neuromorphic systems, ranging from machine learning, computation-in-memory, to full brain emulating systems. These applications are based on different functionalities of the memristive devices (as e. g. analog multi-level programming), and set different - but often not yet fully explored-reliability requirements. Interestingly, however, some of these neuromorphic circuits are more resilient to device failure, while major memory reliability threats as stochasticity, variability and noise even may become assets for building self-learning and predictive systems.

关键词： memristive device neuromorphic computing machine learning deep learning spiking neural networks computation-in-memory vector-matrix-multiplication reliability

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Brief Announcement: Parallel Transitive Closure Within 3D Crosspoint memory 18

Brief Announcement: Parallel Transitive Closure Within 3D Cr...

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30th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA)

作者： Velasquez, Alvaro Jha, Sumit Kumar Univ Cent Florida Dept Comp Sci Orlando FL 32816 USA

ISBN: (纸本)9781450357999

The infamous memory-processor bottleneck has motivated the search for logic-in-memory architectures. In this paper, we demonstrate how the transitive closure problem can be solved through in-memory computing within a 3D crosspoint memory. The proposed architecture requires only two layers of 1-diode 1-resistor (1D1R) interconnects and external feedback loops.

关键词： computation-in-memory in-memory computing rram 3d xpoint transitive closure logic-in-memory matrix multiplication

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A 28 nm Configurable memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-memory

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2016年第4期51卷 1009-1021页

作者： Jeloka, Supreet Akesh, Naveen Bharathwaj Sylvester, Dennis Blaauw, David Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA Oracle Santa Clara CA 95054 USA

Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2-5x and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search operations. In addition, the configurable memory can perform bit-wise logical operations: "AND" and "NOR" on two or more words stored within the array. Thus, the configurable memory with CAM and logical function capability can be used to off-load specific computational operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64x64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A logical operation between two 64 bit words achieves 787 MHz at 1 V.

关键词： computation-in-memory configurable memory content addressable memory (CAM) reconfigurable sense amplifier SRAM

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