Most common uses of negatively weighted bits (negabits), normally assuming arithmetic value 21(0) for logical 1(0) state, are as the most significant bit of 2's-complement numbers and negative component in binary ...
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Most common uses of negatively weighted bits (negabits), normally assuming arithmetic value 21(0) for logical 1(0) state, are as the most significant bit of 2's-complement numbers and negative component in binary signed-digit (BSD) representation. More recently, weighted bit-set (WBS) encoding of generalised digit sets and practice of inverted encoding of negabits (IEN) have allowed for easy handling of any equally weighted mix of negabits and ordinary bits (posibits) via standard arithmetic cells (e.g., half/full adders, compressors, and counters), which are highly optimised for a host of simple and composite figures of merit involving delay, power, and area, and are continually improving due to their wide applicability. In this paper, we aim to promote WBS and IEN as new design concepts for designers of computer arithmetic circuits. We provide a few relevant examples from previously designed logical circuits and redesigns of established circuits such as 2's-complement multipliers and modified booth recoders. Furthermore, we present a modulo-(2(n) + 1) multiplier, where partial products are represented in WBS with IEN. We show that by using standard reduction cells, partial products can be reduced to two. The result is then converted, in constant time, to BSD representation and, via simple addition, to final sum.
This paper presents a highly area-efficient CMOS carry-select adder (CSA) with a regular and iterative-shared transistor structure very suitable for implementation in VLSI. This adder is based on both a static and com...
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This paper presents a highly area-efficient CMOS carry-select adder (CSA) with a regular and iterative-shared transistor structure very suitable for implementation in VLSI. This adder is based on both a static and compact multi-output carry look-ahead (CLA) circuit and a very simple select circuit. Comparisons with other representative 32-bit CSAs show that the proposed adder reduces the area by between 25 and 16%, the number of transistors by between 43 and 30%, and the dynamic power supply between 35 and 16%, while maintaining a high speed. (C) 2004 Elsevier Ltd. All rights reserved.
作者：
KANTABUTRA, VDept. of Comput. Sci.
State Univ. of New York Brockport NY USA Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions
We present a very fast adder for double-precision mantissas, which is an improvement on Lynch and Swartzlander's Spanning Tree Carry Lookahead Adder or Redundant Cell Adder (IEEE Trans. Comput., Aug. 1992 and IEEE...
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We present a very fast adder for double-precision mantissas, which is an improvement on Lynch and Swartzlander's Spanning Tree Carry Lookahead Adder or Redundant Cell Adder (IEEE Trans. Comput., Aug. 1992 and IEEE ARITH10 Symp., 1991) which was implemented in AMD's Am29050 microprocessor. Our adder is faster than theirs mainly because we use Manchester carry chains of various lengths instead of chains of all the same length.
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