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8th Electron Devices Technology & Manufacturing Conference (EDTM)

作者： Xu, Weikai Luo, Jin Fu, Boyi Fu, Zhiyuan Wang, Kaifeng Su, Chang Huang, Qianqian Huang, Ru Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Beijing Adv Innovat Ctr Integrated Circuits Beijing 100871 Peoples R China Chinese Inst Brain Res Beijing 102206 Peoples R China

ISBN: (纸本)9798350383089;9798350371529

In this work, a novel small-signal ferroelectric (FE) memcapacitor (FeCap) based capacitive computing-in-memory (CIM) for quantized neural networks (QNNs) is proposed and experimentally demonstrated. By utilizing the non-monotonic FE small-signal capacitance for signed weight storage and non-destructive readout for input activation, the linearly non-separable signed binary multiplication is implemented in single one FeCap without static DC power consumption, enabling binary neural network with binarized weight and activation. Moreover, by further utilizing the multilevel FE small-signal capacitance with different polarization states, the signed multiplication operation with 3-bit weights is experimentally demonstrated in one FeCap, enabling higher precision of quantized-weight. Based on the proposed FE capacitive CIM, high-accuracy pattern recognition of QNN is demonstrated with 280x/200x/40x lower energy consumption compared with SRAM-/RRAM-/FeFET-based resistive CIM, showing its high potential for area- and energy-efficient edge AI.

关键词： Ferroelectric small-signal capacitance computing in memory quantized neural network

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VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for computing-in-memory Accelerators

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第10期69卷 4028-4041页

作者： Jing, Zhaokun Yan, Bonan Yang, Yuchao Huang, Ru Peking Univ Sch Integrated Circuits Key Lab Microelect Devices & Circuits MOE Beijing 100871 Peoples R China Peking Univ Sch Integrated Circuits Inst Artificial Intelligence Beijing 100871 Peoples R China Peking Univ Key Lab Microelect Devices & Circuits MOE Sch Integrated Circuits Inst Artificial Intelligence Beijing 100871 Peoples R China Peking Univ Ctr Brain Inspired Chips Inst Artificial Intelligence Beijing 100871 Peoples R China Chinese Inst Brain Res CIBR Ctr Brain Inspired Intelligence Beijing 102206 Peoples R China Beijing Acad Artificial Intelligence Beijing 100084 Peoples R China

Non-volatile memory (NVM) such as RRAM and PCM has become the key component in high energy efficiency computing-in-memory (CIM) architectures. However, the computing accuracy and energy efficiency improvement of conventional 1T1R RRAM array based current sensing CIM scheme is hindered by device variation and large output current. In this work, we propose a voltage sensing differential column architecture (VSDCA) based on 1T2R RRAM array for binary memory and CIM applications. The memory mode of VSDCA macro can improve 1.12x to 5.29x relative read margin compared to conventional 1T1R current sensing memory. The computing mode supports 8-bit input, 9-bit weight and 18-bit output high precision and rows fully parallel computing. The VSDCA macro design is evaluated under SMIC 40 nm technology node, the energy efficiency for the high precision CIM reaches 39.52 TOPS/W. The CIFAR10 inference accuracy of the simulated VGG16 and ResNet18 model is 85.91% and 89.32% respectively.

关键词： RRAM computing in memory neural networks high energy efficiency voltage sensing

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A Novel Encrypted computing-in-memory (eCIM) by Implementing Random Telegraph Noise (RTN) as Keys Based on 55 nm NOR Flash Technology

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON DEVICE LETTERS 2022年第9期43卷 1455-1458页

作者： Feng, Yang Wu, Jixuan Zhan, Xuepeng Liu, Jing Sun, Zhaohui Zhang, Junyu Kobayashi, Masaharu Chen, Jiezhi Shandong Univ Sch Informat Sci & Engn ISE Qingdao 266237 Peoples R China Chinese Acad Sci Key Lab Microelect Devices & Integrated Techno Inst Microelect Beijing 100029 Peoples R China Neumem Co Ltd Hefei 241060 Peoples R China Univ Tokyo Inst Ind Sci Tokyo 1138654 Japan

A novel encrypted computing-in-memory (eCIM) architecture is proposed based on 55nm NOR Flash memory technology, wherein the current fluctuations caused by random telegraph noise (RTN) in flash cells are utilized as the intrinsic encryption source. Furthermore, aiming at the low-power consumption with high bit-density, the near-subthreshold region of the flash cell is used for 2-bit/cell operation. It is demonstrated that, in the designed 32-bit floating-point (FP) calculation architecture, ultra-low power dissipation (0.24 pJ/bit) can be achieved with high calculation accuracies after the decryption.

关键词： Encryption Fluctuations Computer architecture Standards Physical unclonable function Threshold voltage Sun NOR flash memory computing in memory encryption random telegraph noise

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Parametric Faults in computing-in-memory Applications of a 4kb Read-Decoupled 8T SRAM Array in 40nm CMOS 7

Parametric Faults in Computing-in-Memory Applications of a 4...

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7th IEEE International Test Conference in Asia (ITC-Asia)

作者： Hong, Hao-Chiao Chen, Chien-Hung Chen, Yu-Wun Natl Yang Ming Chiao Tung Univ Inst Elect & Comp Engn Hsinchu 300093 Taiwan

ISBN: (纸本)9798350312812

computing-in-memory (CIM) circuits can energy-efficiently conduct the massive multiply-and-accumulate (MAC) computations required by artificial neural networks (ANNs). However, the CIM's resolution relies on a fundamental assumption of the CIM design: all memory cells output the same current to their read bitlines (RBLs) given the same read wordline voltage and stored weight bit. In practice, parametric faults due to the devices' intrinsic process variations may introduce significant errors to the MAC results. This work implements accurate test circuits with a 4kb read-decoupled 8T (RD8T) SRAM macro in 40nm CMOS to investigate the parametric faults caused by the intrinsic process variations. Our measurement results reveal the detailed spatial distribution of the RD8T cells' output currents and suggest that the CIM accuracy can be improved by calibrating the gain errors of the RBLs.

关键词： parametric faults analog fault model computing in memory current characterization industry innovation and infrastructure

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A 129.83 TOPS/W Area Efficient Digital SOT/STT MRAM-Based computing-In-memory for Advanced Edge AI Chips 56

A 129.83 TOPS/W Area Efficient Digital SOT/STT MRAM-Based Co...

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56th IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Lu, Lu Mani, Aarthy Anh Tuan Do Agcy Sci Technol & Res Inst Microelect Singapore Singapore

ISBN: (纸本)9781665451093

This paper proposes a spin-orbit torque (SOT) magnetoresistive random access memory (MRAM)-based digital computing in memory (CIM) structure for advanced CIM edge AI chips. To avoid frequent data reloading and reduce the area overhead caused by the large transistor in the write path, 11 transistors and 4 shared heavy metal (HM) SOT MRAM bitcell is proposed. It contains 4b weight in a single cell in a compact area able to hold a large capacity with reduced latency. Compared to the previous SRAM+NOR digital CIM design, the SOT/STT MRAM CIM designs occupy only 40% and 30% bitcell area respectively. Additionally, SOT MRAM has a 1.16% leakage current of SRAM at the TT corner at room temperature. The proposed design is verified using statistic simulations in 28nm technology. It achieves 129.83 TOPS/W at 1b/1b/8b precision.

关键词： computing in memory SOT STT MRAM neural network

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Challenges and Opportunities for computing-in-memory Chips 23

Challenges and Opportunities for Computing-in-Memory Chips

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International Symposium on Physical Design (ISPD)

作者： Qiu, Xiang East China Normal Univ Shanghai Peoples R China

ISBN: (纸本)9781450399784

In recent years, artificial neural networks have been applied to many scenarios, from daily life applications like face detection, to industry problems like placement and routing in physical design. Neural network inference mainly contains multiply-accumulate operations, which requires huge amount of data movement. Traditional Von-Neumann architecture computers are inefficient for neural networks as they have separate CPU and memory, and data transfer between them costs excessive energy and performance. To address this problem, in-memory or near-memory computing have been proposed and attracted much attention in both academic and industry. In this talk, we will give a brief review of non-volatile memory crossbar-based computing-in-memory architecture. Next, we will demonstrate the challenges for chips with such architecture to replace current CPUs/GPUs for neural network processing, from an industry perspective. Lastly, we will discuss possible solutions for those challenges.

关键词： computing in memory neural network architectures analog computing non-volatile memory

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An Efficient Flash-Based computing-in-memory (CIM) Demonstration of High-Precision (32-bit) Nonlinear Partial Differential Equation (PDE) Solver With Ultra-High Endurance and Reliability

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年

作者： Feng, Yang Sun, Zhaohui Wang, Chengcheng Guo, Xinyi Mei, Junyao Qi, Yueran Liu, Jing Zhang, Junyu Wu, Jixuan Zhan, Xuepeng Huang, Peng Chen, Jiezhi Shandong Univ Sch Informat Sci & Engn ISE Qingdao 266237 Peoples R China Chinese Acad Sci Inst Microelect Key Lab Microelect Devices & Integrated Technol Beijing 100045 Peoples R China NeuMem Co Ltd Hefei 266237 Peoples R China Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China

Solving partial differential equations (PDEs) requires precise numerical iterations that impose significant demands on computational resources and memory capacities, which can be addressed by adopting computing-in-memory (CIM) architecture to reduce the latency and power consumption during data transmission. Among PDEs, nonlinear PDEs present heightened complexities in both analytical investigations and numerical simulations as the presence of nonlinear terms introduces intricate dynamics and mathematical intricacies. The high-precision requirements of PDE solvers, particularly for nonlinear PDE solvers, pose challenges in constructing CIM PDE solvers. In this work, a flash-based high-precision PDE solver has been demonstrated to solve the intractable nonlinear partial differential equation. It's based on 55nm NOR flash technology with well-optimized Program/Erase (PE) schemes. Utilizing the proposed optimization scheme, the PE endurance can be largely enhanced up to 10(10) cycles, which is a record high with suppressed cell degradation and robust reliabilities. Then, applying the Fourier neural operator (FNO) to the optimized flash-based high-precision CIM (32-bit) in the hardware system, a series of nonlinear PDEs can be solved with similar to 2TOPS/W high energy efficiency, which is similar to 110x higher than CPU. Our optimization strategies make it feasible to use flash-based CIM for high-precision computing with frequent weight updating and the demonstrated PDE solver provides an energy-saving solution to implement general-purpose computation tasks.

关键词： NOR flash memory computing in memory general computing non-linear partial differential solver flash memory circuit

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Flash-Based computing-in-memory Architecture to Implement High-Precision Sparse Coding

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MICROMACHINES 2023年第12期14卷 2190-2190页

作者： Qi, Yueran Feng, Yang Wang, Hai Wang, Chengcheng Bai, Maoying Liu, Jing Zhan, Xuepeng Wu, Jixuan Wang, Qianwen Chen, Jiezhi Shandong Univ Sch Informat Sci & Engn Qingdao 266237 Peoples R China Chinese Acad Sci Key Lab Microelect Devices & Integrated Technol Inst Microelect Beijing 100029 Peoples R China

To address the concerns with power consumption and processing efficiency in big-size data processing, sparse coding in computing-in-memory (CIM) architectures is gaining much more attention. Here, a novel Flash-based CIM architecture is proposed to implement large-scale sparse coding, wherein various matrix weight training algorithms are verified. Then, with further optimizations of mapping methods and initialization conditions, the variation-sensitive training (VST) algorithm is designed to enhance the processing efficiency and accuracy of the applications of image reconstructions. Based on the comprehensive characterizations observed when considering the impacts of array variations, the experiment demonstrated that the trained dictionary could successfully reconstruct the images in a 55 nm flash memory array based on the proposed architecture, irrespective of current variations. The results indicate the feasibility of using Flash-based CIM architectures to implement high-precision sparse coding in a wide range of applications.

关键词： computing in memory sparse coding image reconstruction online training flash memory

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Consistency Analysis and Priorities Deriving for Pythagorean Fuzzy Preference Relation in the "computing in memory"

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IEEE ACCESS 2020年 8卷 156972-156985页

作者： Zhang, Li Zhou, Ligang Yang, Kaifang Anhui Univ Sch Elect & Informat Engn Hefei 230601 Peoples R China Anhui Univ Sch Math Sci Hefei 230601 Peoples R China

Pythagorean fuzzy set, characterized by membership function and non-membership function, has received increasing attention in recent years. In this paper, a new approach to decision making is proposed based on Pythagorean fuzzy preference relation and its additive consistency. Firstly, the concepts of Pythagorean fuzzy preference relations and its additive consistency are introduced, and followed by a discussion of their desirable properties. Then, a linear goal programming model is proposed to determine the consistency of PFPRs. For the PFPRs that does not satisfy the consistency, the consistency index is defined to measure the degree of consistency, and a consistency adjustment algorithm is proposed. Finally, based on the additive consistency, a new algorithm for decision making is presented. An example of CIM(computing in memory) is provided, and in comparison with other methods, the validity and rationality of the proposed method are verified.

关键词： Additives Decision making Fuzzy sets Programming Uncertainty Linguistics Indexes Pythagorean fuzzy preference relations additive consistency consistency adjustment decision making computing in memory

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Mapping Binary ResNets on computing-In-memory Hardware with Low-bit ADCs

Mapping Binary ResNets on Computing-In-Memory Hardware with ...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Kim, Yulhwa Kim, Hyungjun Park, Jihoon Oh, Hyunmyung Kim, Jae-Joon Pohang Univ Sci & Technol POSTECH Pohang South Korea

ISBN: (纸本)9783981926354

Implementing binary neural networks (BNNs) on computing-in-memory (CIM) hardware has several attractive features such as small memory requirement and minimal overhead in peripheral circuits such as analog-to-digital converters (ADCs). On the other hand, one of the downsides of using BNNs is that it degrades the classification accuracy. Recently, ResNet-style BNNs are gaining popularity with higher accuracy than conventional BNNs. The accuracy improvement comes from the high-resolution skip connection which binary ResNets use to compensate the information loss caused by binarization. However, the high-resolution skip connection forces the CIM hardware to use high-bit ADCs again so that area and energy overhead becomes larger. In this paper, we demonstrate that binary ResNets can be also mapped on CIM with low-bit ADCs via aggressive partial sum quantization and input-splitting combined with retraining. As a result, the key advantages of BNN CIM such as small area and energy consumption can be preserved with higher accuracy.

关键词： NN accelerator computing in memory analog computing hardware-NN co-design

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