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Mitigating methodology of hardware non-ideal characteristics for non-volatile memory based neural networks

Science China(Information Sciences) 2025年第2期68卷 307-321页

作者： Lixia HAN Peng HUANG Yijiao WANG Zheng ZHOU Haozhang YANG Yiyang CHEN Xiaoyan LIU Jinfeng KANG School of Integrated Circuits Peking University Beijing Advanced Innovation Center for Integrated Circuits School of Integrated Circuit Science and Engineering Beihang University

Non-volatile memory-based computing-in-memory(nvCIM) paradigm has been extensively studied to boost the energy efficiency of neural network accelerators in edge applications. However, the degradation of inference accuracy induced by the non-ideal characteristics across circuits, arrays, and devices is becoming a crucial issue. In this work, we establish a hardware characteristic behavior model to analyze the impact of nvCIM non-ideal characteristics on neural network *** we propose a hardware aware training and weight mapping correction methods to mitigate inference accuracy *** simulation verification, about 95% inference accuracy degradation is recovered by adopting the proposed mitigation method for various non-ideal characteristics and various neural network models. The feasibility of the proposed method is further proved in an experimental example with a flash-based LeNet recognition system.

关键词： computing in memory neural network accelerators non-volatile memory hardware non-ideal characteristics software-hardware co-design

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The show must go on: a reliability assessment platform for resistive random access memory crossbars

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PHILOSOPHICAL TRANSACTIONS OF THE ROYAL SOCIETY A-MATHEMATICAL PHYSICAL AND ENGINEERING SCIENCES 2025年第2288期383卷 20230387页

作者： Pelke, Rebecca Staudigl, Felix Thomas, Niklas Hossein, Mohammed Bosbach, Nils Cubero-Cascante, Jose Leupers, Rainer Joseph, Jan Moritz Rhein Westfal TH Aachen Aachen Germany

Resistive random access memory (ReRAM) holds promise for building computing-in-memory (CIM) architectures to execute machine learning (ML) applications. However, existing ReRAM technology faces challenges such as cell and cycle variability, read-disturb and limited endurance, necessitating improvements in devices, algorithms and applications. Understanding the behaviour of ReRAM technologies is crucial for advancement. Existing platforms can either only characterize single cells and do not support CIM operations, or lack a comprehensive software stack for simple system integration. This article introduces NeuroBreakoutBoard (NBB), a versatile, integrable and portable instrumentation platform for ReRAM crossbars. The platform features a software stack enabling experiments via Python from a host PC. In a case study, we demonstrate the capabilities of NBB by conducting diverse experiments on TiN/Ti/HfO2/TiN cells. Our results show that NBB can characterize individual cells and perform CIM operations with a relative measurement error below 2%.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.

关键词： ReRAM computing in memory reliability machine learning

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Investigation on the 3D Memristor Array Architecture for 3D Reservoir computing System Implementation

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON DEVICE LETTERS 2024年第8期45卷 1445-1448页

作者： Sun, Wenxuan Yu, Jie Dong, Danian Zheng, Xu Lai, Jinru Fan, Shaoyang Wang, Hongzhou Gao, Jianfeng Liu, Junfeng Xu, Xiaoxin Chinese Acad Sci Inst Microelect State Key Lab Fabricat Technol Integrated Circuits Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China Fudan Univ Frontier Inst Chip & Syst State Key Lab Integrated Chip & Syst Shanghai 200433 Peoples R China

Three-dimensional reservoir computing (3D RC) system is an energy efficient recurrent neural network for achieving high area efficiency. Considering the physical implementation of 3D RC by memristor, 3D Vertical Memristor Array (3D-VMA) is proved a more economical and reliable approach than 3D Cross-point Memristor Array (3D-CMA). Due to the natural competitive parallel structure in the 3D-VMA, the cumulative effect of the devices is better, which improves the differentiation between reservoir states. Meanwhile, the system noise is reduced since the Cycle-to-Cycle (C-to-C) variation is well controlled. The Mackey-Glass (M-G) prediction shows that the prediction performance of RC system implemented by the 3D-VMA improves by 4.2 times compared with that by 3D-CMA. The highly robust 3D vertical architecture proves the novel approach to realize high-performance 3D RC system.

关键词： Three-dimensional displays Reservoirs Memristors Computer architecture Voltage Performance evaluation Hardware 3D vertical memristor array 3D reservoir computing real-time information processing computing in memory

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A high charge-discharge stability SRAM 10T1C XOR CIM macro applied in BCAM and Hamming distance

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MICROELECTRONICS JOURNAL 2025年 161卷

作者： Liu, Li Hu, Wei Yang, Zhen Wei, Yiming Peng, Chunyu Wu, Xiulong Lin, Zhiting Lu, Wenjuan Zhou, Yongliang Chen, Junning Anhui Univ Sch Integrated Circuits Hefei 230601 Peoples R China Anhui High Performance Integrated Circuit Engn Res Hefei Peoples R China

With the rapid development of artificial intelligence, there has been an increasing demand for computing speed and power. At the same time, computing stability is also essential. We proposed a high charge-discharge stability SRAM 10T1C XOR CIM macro. By decoupling Q and QB nodes, the XOR CIM is completed within the unit without affecting storage stability. Based on the XOR operation, BCAM and Hamming distance are also performed on multiple units in the column. According to the post-layout simulation of 28 nm CMOS process, the standard deviation of 10T1C charge-discharge stability is only 1.236 mu V at 0.9V, which 6T, 8T, 9T, and 10T are 9.164 mV, 10.329 mV, 16.084 mV and 9.567 mV, respectively. At 0.6V, the accuracy of BCAM reaches 99 %, which is improved by 153.8 %, 291.3 %, 175.8 %, and 206.5 %;the accuracy of Hamming distance reaches 96.8 %, which is improved by 16.3 %, 17.8 %, 16.0 %, and 16.1 %, respectively. This work combine KNN algorithm and Hamming distance to the prediction accuracy of 95.76 % on the MNIST dataset.

关键词： von Neumann bottleneck computing in memory XOR BCAM Hamming distance

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Type-Theory of Algorithms with Chain-Free memory 21st

Type-Theory of Algorithms with Chain-Free Memory

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21st International Symposium on Distributed computing and Artificial Intelligence

作者： Loukanova, Roussanka Bulgarian Acad Sci Inst Math & Informat Sofia Bulgaria

ISBN: (纸本)9783031820724;9783031820731

The results of the stepwise computations are saved in memory slots, for possible reuse. The extended calculus reduces unnecessary iterations of assignments, which are chains of unnecessary assignments, by copying values of terms from one memory slot to another, without any essential algorithmic changes. The primary applications of the chain-free type theory of recursion are for computational semantics of formal and natural languages, including programming languages and compilers.

关键词： formal language algorithms lambda recursion reduction calculus computing in memory memorisation chain-free computation

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AFPR-CIM: An Analog-Domain Floating-Point RRAM-based Compute-In-memory Architecture with Dynamic Range Adaptive FP-ADC

AFPR-CIM: An Analog-Domain Floating-Point RRAM-based Compute...

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27th Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Liu, Haobo Qian, Zhengyang Wu, Wei Ren, Hongwei Liu, Zhiwei Ni, Leibin Univ Elect Sci & Technol China Shenzhen Inst Adv Study Shenzhen Peoples R China Huawei Technol Co Ltd Labs 2012 Cent Res Inst Shenzhen Peoples R China Hong Kong Univ Sci & Technol Guangzhou MICS Thrust Guangzhou Peoples R China

ISBN: (纸本)9798350348606;9783981926385

Power consumption has become the major concern in neural network accelerators for edge devices. The novel non-volatile-memory (NVM) based computing-in-memory (CIM) architecture has shown great potential for better energy efficiency. However, most of the recent NVM-CIM solutions mainly focus on fixed-point calculation and are not applicable to floating-point (FP) processing. In this paper, we propose an analog-domain floating-point CIM architecture (AFPR-CIM) based on resistive random-access memory (RRAM). A novel adaptive dynamic-range FP-ADC is designed to convert the analog computation results into FP codes. Output current with high dynamic range is converted to a normalized voltage range for readout, to prevent precision loss at low power consumption. Moreover, a novel FP-DAC is also implemented which reconstructs FP digital codes into analog values to perform analog computation. The proposed AFPR-CIM architecture enables neural network acceleration with FP8 (E2M5) activation for better accuracy and energy efficiency. Evaluation results show that AFPR-CIM can achieve 19.89 TFLOPS/W energy efficiency and 1474.56 GOPS throughput. Compared to traditional FP8 accelerator, digital FP-CIM, and analog INT8-CIM, this work achieves 4.135x, 5.376x, and 2.841x energy efficiency enhancement, respectively.

关键词： computing in memory analog domain floating-point RRAM dynamic range adaptive

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Architecture Design for Pedestrian Detection Based on memory Grid Occupancy and Data Reuse

Architecture Design for Pedestrian Detection Based on Memory...

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International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC)

作者： Yul, Ke Baek, JangWoo Yusupbaev, Bobokhon Choi, Jun Rim Kyungpook Natl Univ Sch Elect & Elect Engn Daegu South Korea Kyungpook Natl Univ Sch Elect Engn Daegu South Korea

ISBN: (纸本)9798350379068;9798350379051

Pedestrian Detection, as an integral component of autonomous driving systems, is directly related to the vehicle safety. However, trapped by the current computing paradigm based on Von Neumann architecture, the traditional design of Pedestrian Detection system faces certain dilemmas in terms of energy consumption and computational efficiency. In this paper, an approach based on memory Grid Occupancy (MGO) and data reuse is proposed to optimize the computational process of the Pedestrian Detection system. The results of the related work indicate that the proposed optimization design in hardware can reduce the data read/write during the execution of the system.

关键词： Pedestrian Detection memory Grid Occupancy Data Reuse computing in memory Position Detection

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Model Inference Optimization on ReRAM-Based Accelerators with Intra- and Inter-OU Similarity

Model Inference Optimization on ReRAM-Based Accelerators wit...

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2nd International Symposium of Electronics Design Automation (ISEDA)

作者： Li, Tao Zhao, Qinghang Xidian Univ Sch Artificial Intelligence Xian Peoples R China

ISBN: (纸本)9798350352047;9798350352030

computing-In-memory (CIM) technology is promising for DNN inference acceleration, in which ReRAM-based crossbars have received extensive attention in various aspects. However, the current model deployment research often neglects the read-write imbalance problem. This work proposes a comprehensive solution of inference optimization for multi-bit ReRAM-based crossbar array accelerator. In fine grain of operation unit (OU), a row and column exchange algorithm called RCSwap is proposed to minimize the difference between the weights before and after update and therefore reduce the program time and energy consumption. And in coarse grain, similarity-based scheduling method is presented to exploit the inter-OU difference for further performance improvement. Experiment results show that the proposed methods combined reduce up to 33% and 34% in time delay and energy consumption for model inference, respectively.

关键词： computing in memory ReRAM with multiple states DNN accelerator deploy scheduling

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A Trainable Synapse Circuit Using a Time-Domain Digital-to-Analog Converter

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2022年第3期42卷 1312-1326页

作者： Uenohara, Seiji Aihara, Kazuyuki Univ Tokyo Inst Ind Sci Meguro Ku 4-6-1 Komaba Tokyo 1538505 Japan Kyushu Inst Technol Grad Sch Life Sci & Syst Engn Wakamatsu Ku 2-4 Hibikino Kitakyushu Fukuoka 8080196 Japan Univ Tokyo Int Res Ctr Neurointelligence Bunkyo Ku 7-3-1 Hongo Tokyo 1138654 Japan

We propose a CMOS synapse circuit using a time-domain digital-to-analog converter (TDAC) for realizing spiking neural network hardware with on-chip learning. A TDAC has the advantages that (i) it can reproduce a post-synaptic potential and (ii) its number of analog components for DA conversion, such as current sources and capacitors, is independent of the bit width. We designed a synapse circuit using TSMC 40 nm technology, and the synaptic weight was updated by the remote supervised method (ReSuMe) or spike timing-dependent plasticity (STDP). The circuit simulation results of the designed circuit show that it can execute ReSuMe and generate the time-window function for STDP with high energy efficiency.

关键词： ReSuMe STDP On-chip learning TDAC computing in memory CIM Spiking neural networks SNNs

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Hardware-Robust In-RRAM-computing for Object Detection

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IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2022年第2期12卷 547-556页

作者： Chiang, Yu-Hsiang Ni, Cheng-En Sung, Yun Hou, Tuo-Hung Chang, Tian-Sheuan Jou, Shyh-Jye Natl Yang Ming Chiao Tung Univ Inst Elect Hsinchu 30010 Taiwan

In-memory computing is becoming a popular architecture for deep-learning hardware accelerators recently due to its highly parallel computing, low power, and low area cost. However, in-RRAM computing (IRC) suffered from large device variation and numerous nonideal effects in hardware. Although previous approaches including these effects in model training successfully improved variation tolerance, they only considered part of the nonideal effects and relatively simple classification tasks. This paper proposes a joint hardware and software optimization strategy to design a hardware-robust IRC macro for object detection. We lower the cell current by using a low word-line voltage to enable a complete convolution calculation in one operation that minimizes the impact of nonlinear addition. We also implement ternary weight mapping and remove batch normalization for better tolerance against device variation, sense amplifier variation, and IR drop problem. An extra bias is included to overcome the limitation of the current sensing range. The proposed approach has been successfully applied to a complex object detection task with only 3.85% mAP drop, whereas a naive design suffers catastrophic failure under these nonideal effects.

关键词： Training Resistance Convolution Computational modeling Task analysis Object detection Hardware computing in memory object detection RRAM

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