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The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2021年第12期68卷 4821-4834页

作者： Ye, Le Wang, Zhixuan Liu, Ying Chen, Peiyu Li, Heyi Zhang, Hao Wu, Meng He, Wei Shen, Linxiao Zhang, Yihan Tan, Zhichao Wang, Yangyuan Huang, Ru Peking Univ Inst Microelect Key Lab Microelect Devices & Circuits MOE Beijing 100871 Peoples R China Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310058 Peoples R China

The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.

关键词： Batteries Artificial intelligence Power demand Internet of Things Energy harvesting Sensors Servers Internet of Things random sparse events light-duty artificial intelligence event-driven level-crossing ADC asynchronous computing in memory spike neural network charge-domain power management energy harvesting evaluation criteria ultralow power energy-efficient

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A high charge-discharge stability SRAM 10T1C XOR CIM macro applied in BCAM and Hamming distance

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MICROELECTRONICS JOURNAL 2025年 161卷

作者： Liu, Li Hu, Wei Yang, Zhen Wei, Yiming Peng, Chunyu Wu, Xiulong Lin, Zhiting Lu, Wenjuan Zhou, Yongliang Chen, Junning Anhui Univ Sch Integrated Circuits Hefei 230601 Peoples R China Anhui High Performance Integrated Circuit Engn Res Hefei Peoples R China

With the rapid development of artificial intelligence, there has been an increasing demand for computing speed and power. At the same time, computing stability is also essential. We proposed a high charge-discharge stability SRAM 10T1C XOR CIM macro. By decoupling Q and QB nodes, the XOR CIM is completed within the unit without affecting storage stability. Based on the XOR operation, BCAM and Hamming distance are also performed on multiple units in the column. According to the post-layout simulation of 28 nm CMOS process, the standard deviation of 10T1C charge-discharge stability is only 1.236 mu V at 0.9V, which 6T, 8T, 9T, and 10T are 9.164 mV, 10.329 mV, 16.084 mV and 9.567 mV, respectively. At 0.6V, the accuracy of BCAM reaches 99 %, which is improved by 153.8 %, 291.3 %, 175.8 %, and 206.5 %;the accuracy of Hamming distance reaches 96.8 %, which is improved by 16.3 %, 17.8 %, 16.0 %, and 16.1 %, respectively. This work combine KNN algorithm and Hamming distance to the prediction accuracy of 95.76 % on the MNIST dataset.

关键词： von Neumann bottleneck computing in memory XOR BCAM Hamming distance

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Using SRAM-based CIM Architecture as the Event Detector for AIoT Applications 8

Using SRAM-based CIM Architecture as the Event Detector for ...

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8th IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW) - Driving World to 5G and Beyond with Consumer Technology

作者： Lu, Chih-Cheng Sulaiman, Muhammad Bintang Gemintang Lin, Chin-Yu Li, Jian-Bai Shih, Cheng-Ming Rih, Wei-Shu Juang, Kai-Cheung Ind Technol Res Inst Zhudong Township Taiwan

ISBN: (纸本)9781665433280

Convolutional neural networks (CNNs) play a key role in deep learning applications. computing-in-memory (CIM) architecture has demonstrated great potential to effectively compute large-scale matrix-vector multiplication. For implementation a CIM-based accelerator, a software and hardware co-design approach have to consider the hardware limitations of the CIM macro to map the weight into the AI edge-devices. In this paper, we proposed a hierarchical AI architecture to optimized the end-to-end system power in the AIoT application. CIM-based architecture for event detection is designed to trigger the next stage precision inference. In the experiment, CIM-aware algorithm with 4-bit activation and 4-bit weight on Hand gesture [2] and Yale face [3] datasets are examined to have >95% accuracy. Profiling tool to analyzed the entry-level CIM architecture are also developed.

关键词： Artificial Internet of Things Convolutional Neural Network computing in memory

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SRAM-Based CIM Architecture Design for Event Detection

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SENSORS 2022年第20期22卷 7854页

作者： Sulaiman, Muhammad Bintang Gemintang Lin, Jin-Yu Li, Jian-Bai Shih, Cheng-Ming Juang, Kai-Cheung Lu, Chih-Cheng Ind Technol Res Inst 195Sect 4Zhongxing Rd Hsinchu 310401 Taiwan

Convolutional neural networks (CNNs) play a key role in deep learning applications. However, the high computational complexity and high-energy consumption of CNNs trammel their application in hardware accelerators. computing-in-memory (CIM) is the technique of running calculations entirely in memory (in our design, we use SRAM). CIM architecture has demonstrated great potential to effectively compute large-scale matrix-vector multiplication. CIM-based architecture for event detection is designed to trigger the next stage of precision inference. To implement an SRAM-based CIM accelerator, a software and hardware co-design approach must consider the CIM macro's hardware limitations to map the weight onto the AI edge devices. In this paper, we designed a hierarchical AI architecture to optimize the end-to-end system power in the AIoT application. In the experiment, the CIM-aware algorithm with 4-bit activation and 8-bit weight is examined on hand gesture and CIFAR-10 datasets, and determined to have 99.70% and 70.58% accuracy, respectively. A profiling tool to analyze the proposed design is also developed to measure how efficient our architecture design is. The proposed design system utilizes the operating frequency of 100 MHz, hand gesture and CIFAR-10 as the datasets, and nine CNNs and one FC layer as its network, resulting in a frame rate of 662 FPS, 37.6% processing unit utilization, and a power consumption of 0.853 mW.

关键词： artificial internet of things computing in memory convolutional neural network

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Valley-Coupled-Spintronic Non-Volatile Memories With Compute-In-memory Support

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2020年 19卷 635-647页

作者： Thirumala, Sandeep Krishna Hung, Yi-Tse Jain, Shubham Raha, Arnab Thakuria, Niharika Raghunathan, Vijay Raghunathan, Anand Chen, Zhihong Gupta, Sumeet Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA Purdue Univ Birck Nanotechnol Ctr W Lafayette IN 47907 USA IBM Thomas J Watson Res Yorktown Hts NY 10598 USA Intel Corp Santa Clara CA 95054 USA

In this work, we propose valley-coupled spin-hall memories based on monolayer WSe2. The key features of the proposed memories are (a) the ability to switch magnets with perpendicular magnetic anisotropy and (b) an integrated gate that can modulate the charge/spin current (I-C/I-S) flow. The former attribute results in high energy efficiency (compared to the Giant-Spin Hall (GSH) effect-based devices with in-planemagnetic anisotropy magnets). The latter feature leads to a compact access-transistor-less memory array design. We experimentally measure the gate controllability of the current as well as the non-local resistance associated with valley-coupled spin-hall effect. Based on the measured data, we develop a simulation framework to propose and analyze single-ended and differential valley-coupled spin-hall effect basedmagnetic memories(VSH-MRAMandDVSH-MRAM, respectively). At the array level, the proposedVSH/DVSH-MRAMs achieve 50%/11% lower write time, 59%/67% lower write energy, 12%/30% lower read time and 35%/41% lower read energy at iso-sensemargin, compared to single-ended/differentialGiant-Spin Hall (GSH/DGSH)-MRAMs. System level evaluation in the context of general-purpose processor and intermittently-powered system shows up to 3.14X and 1.98X better energy efficiency for the proposed (D)VSH-MRAMs over (D)GSH-MRAMs respectively. Further, the differential sensing of the proposed DVSH-MRAM leads to natural and simultaneous in-memory computation of bit-wise AND and NOR logic functions. Using this feature, we design a computation-in-memory (CiM) architecture that performs Boolean logic and addition with a single array access. System analysis performed by integrating our DVSH-MRAM: CiM in the Nios II processor shows up to 2.57X total energy savings, compared to DGSH-MRAM: CiM.

关键词： computing in memory magnetic RAM non-volatile memory spin currents VSH/GSH effect

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Reliability aspects of binary vector-matrix-multiplications using ReRAM devices

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NEUROMORPHIC computing AND ENGINEERING 2022年第3期2卷 034001-034001页

作者： Bengel, Christopher Mohr, Johannes Wiefels, Stefan Singh, Abhairaj Gebregiorgis, Anteneh Bishnoi, Rajendra Hamdioui, Said Waser, Rainer Wouters, Dirk Menzel, Stephan Rhein Westfal Techn Hsch RWTH Aachen Univ Inst Mat Elect Engn & Informat Technol 2 Aachen Germany Rhein Westfal Techn Hsch RWTH Aachen Univ Julich Aachen Res Alliance JARA Fit Aachen Germany Forschungszentrum Julich Peter Grunberg Inst PGI 7 Julich Germany JARA FIT Julich Germany Delft Univ Technol Comp Engn Dept NL-2628 CD Delft Netherlands Forschungszentrum Julich Peter Grunberg Inst PGI 10 Julich Germany

Computation-in-memory using memristive devices is a promising approach to overcome the performance limitations of conventional computing architectures introduced by the von Neumann bottleneck which are also known as memory wall and power wall. It has been shown that accelerators based on memristive devices can deliver higher energy efficiencies and data throughputs when compared with conventional architectures. In the vast multitude of memristive devices, bipolar resistive switches based on the valence change mechanism (VCM) are particularly interesting due to their low power operation, non-volatility, high integration density and their CMOS compatibility. While a wide range of possible applications is considered, many of them such as artificial neural networks heavily rely on vector-matrix-multiplications (VMMs) as a mathematical operation. These VMMs are made up of large numbers of multiplication and accumulation (MAC) operations. The MAC operation can be realised using memristive devices in an analog fashion using Ohm's law and Kirchhoff's law. However, VCM devices exhibit a range of non-idealities, affecting the VMM performance, which in turn impacts the overall accuracy of the application. Those non-idealities can be classified into time-independent (programming variability) and time-dependent (read disturb and read noise). Additionally, peripheral circuits such as analog to digital converters can introduce errors during the digitalization. In this work, we experimentally and theoretically investigate the impact of device- and circuit-level effects on the VMM in a VCM crossbars. Our analysis shows that the variability of the low resistive state plays a key role and that reading in the RESET direction should be favored to reading in the SET direction.

关键词： computing in memory memristor ReRAM circuit design compact modelling vector-matrix-multiplication dot-product

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Towards State-Aware Computation in ReRAM Neural Networks 57

Towards State-Aware Computation in ReRAM Neural Networks

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57th ACM/IEEE Design Automation Conference (DAC)

作者： He, Yintao Wang, Ying Zhao, Xiandong Li, Huawei Lit, Xiaowei Chinese Acad Sci Inst Comp Technol SKLCA Beijing 100190 Peoples R China Univ Chinese Acad Sci Beijing 100049 Peoples R China Peng Cheng Lab Shenzhen Peoples R China

ISBN: (纸本)9781728110851

Resistive RAM (ReRAM) is a promising device to realize the computing in memory (CiM) architecture, suitable for power-constrained IoT systems. Because of low leakage, the dot-production operations in ReRAM crossbars dominate the chip power, especially when implementing low-precision neural networks. This work investigates the correlation between the cell resistance state and the crossbar operation power, and proposes a State-Aware ReRAM Accelerator (SARA) architecture for energy-efficient neural networks. With the proposed state-aware network training and mapping strategy, crossbars in the ReRAM accelerator can perform in a lower-power state. The evaluation shows that our design reduces 47% energy over the baseline without compromising the network accuracy.

关键词： ReRAM low power computing in memory binary networks

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Algorithm-Hardware Co-Optimization for Neural Network Efficiency Improvement

Algorithm-Hardware Co-Optimization for Neural Network Effici...

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作者： Yang, Qing Duke University

学位级别：Ph.D.

Deep neural networks (DNNs) are tremendously applied in the artificial intelligence field. While the performance of DNNs is continuously improved by more complicated and deeper structures, the feasibility of deployment on edge devices remains a critical problem. In this thesis, we present algorithm-hardware co-optimization approaches to address the challenges of efficient DNN deployments from three aspects: 1) save computational cost, 2) save memory cost, and 3) save data movements. First, we present a joint regularization technique to advance the compression beyond the weights to neuron activations. By distinguishing and leveraging the significant difference among neuron responses and connections during learning, the jointly pruned network, namely JPnet, optimizes the sparsity of activations and weights. Second, to structurally regulate the dynamic activation sparsity (DAS), we propose a generic low-cost approach based on winners-take-all (WTA) dropout technique. The network enhanced by the proposed WTA dropout, namely DASNet, features structured activation sparsity with an improved sparsity level, which can be easily utilized to achieve acceleration on conventional embedded systems. The effectiveness of JPNet and DASNet has been thoroughly evaluated through various network models with different activation functions and on different datasets. Third, we propose BitSystolic, a neural processing unit based on a systolic array structure, to fully support the mixed-precision inference. In BitSystolic, the numerical precision of both weights and activations can be configured in the range of 2b~8b, fulfilling different requirements across mixed-precision models and tasks. Moreover, the design can support various data flows presented in different types of neural layers and adaptively optimize the data reuse by switching between the matrix-matrix mode and vector-matrix mode. We designed and fabricated the proposed BitSystolic in the 65nm process. Our measurement results sho

关键词： Computer engineering computing in memory deep neural network joint regularization mixed-precision inference model compression WTA dropout

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Recent Advances in Compute-in-memory Support for SRAM Using Monolithic 3-D Integration

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IEEE MICRO 2019年第6期39卷 28-37页

作者： Zhang, Zhixiao Si, Xin Srinivasa, Srivatsa Ramanathan, Akshay Krishna Chang, Meng-Fan Natl Tsing Hua Univ Elect Engn Hsinchu Taiwan Fuzhou Univ Fuzhou Fujian Peoples R China Natl Tsing Hua Univ Hsinchu Taiwan Penn State Univ State Coll PA USA Penn State Univ Elect Engn State Coll PA USA

computing-in-memory (CiM) is a popular design alternative to overcome the von Neumann bottleneck and improve the performance of artificial intelligence computing applications. Monolithic three-dimensional (M3D) technology is a promising solution to extend Moore's law through the development of CiM for data-intensive applications. In this article, we first discuss the motivation and challenges associated with two-dimensional CiM designs, and then examine the possibilities presented by emerging M3D technologies. Finally, we review recent advances and trends in the implementation of CiM using M3D technology.

关键词： Artificial Intelligence Electronic Engineering computing memory Architecture Monolithic Integrated Circuits SRAM Chips computing in memory Von Neumann Bottleneck Three Dimensional Technology M 3 D Moores Law Two Dimensional Ci M Designs Compute In memory Support SRAM Monolithic 3 D Integration Artificial Intelligence computing Silicon Random Access memory Logic Gates MOSFET memory Management

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A 307-fps 351.7-GOPs/W Deep Learning FPGA Accelerator for Real-time Scene Text Recognition 18

A 307-fps 351.7-GOPs/W Deep Learning FPGA Accelerator for Re...

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International Conference on Field-Programmable Technology (ICFPT)

作者： Zhao, Shirui An, Fengwei Yu, Hao Southern Univ Sci & Technol Sch Microelect Shenzhen Peoples R China

ISBN: (纸本)9781728129433

FPGA-based deep learning accelerator has become important for high throughput and low power inference at edges. In this paper, we have developed a computing-in-memory (CIM) accelerator using the binary SegNet (BSEG) for real-time scene text recognition (STR) at edges. The accelerator can perform highly efficient pixel-wise character classification under CIM architecture with massive bit-level parallelism as well as optimized pipeline for low latency at critical path. The BSEG is obtained during training with a small model size of 2.1MB as well as a high classification accuracy over 90% on ICDAR-03 and ICDAR-13 datasets. The RTL-level realized FPGA-accelerator can process the STR with an energy-efficiency of 351.7 GOPs/W and a throughput of 307 fps for processing one frame of 128x32 pixels in latency of 3.875 ms.

关键词： deep learning accelerator encoder-decoder neural network trained quantization computing in memory

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