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concurrent error detection in wavelet lifting transforms

IEEE TRANSACTIONS ON COMPUTERS 2004年第10期53卷 1291-1302页

作者： Redinbo, GR Nguyen, C Univ Calif Davis Dept Elect & Comp Engn Livermore CA 95616 USA

Wavelet transforms, central to multiresolution signal analysis and important in the JPEG2000 image compression standard, are quite susceptible to computer-induced errors because of their pipelined structure and multirate processing requirements. Such errors emanate from computer hardware, software bugs, or radiation effects from the surrounding environment. Implementations use lifting schemes, which employ update and prediction estimation stages, and can spread a single numerical error caused by failures to many output transform coefficients without any features to warn data users. This paper proposes an efficient method to detect the arithmetic errors using weighted sums of the wavelet coefficients at the output compared with an equivalent parity value derived from the input data. Two parity values may straddle a complete multistage transform or several values may be used, each pair covering a single stage. There is greater error-detecting capability at only a slight increase in complexity when parity pairs are interspersed between stages. With the parity weighting design scheme, a single error introduced at a lifting section can be detected. The parity computation operation is properly viewed as an inner product between weighting values and the data, motivating the use of dual space functionals related to the error gain matrices. The parity weighting values are generated by a combination of dual space functionals. An iterative procedure for evaluating the design of the parity weights has been incorporated in Matlab code and simulation results are presented.

关键词： wavelet transforms concurrent error detection weighted sum parity real number codes algorithm-based fault tolerance error gain matrices dual space functionals biorthogonality

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concurrent error detection in Montgomery Multiplication over Binary Extension Fields

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IEEE TRANSACTIONS ON COMPUTERS 2011年第9期60卷 1341-1353页

作者： Hariri, Arash Reyhani-Masoleh, Arash Univ Western Ontario Dept Elect & Comp Engn Fac Engn London ON N6A 5B9 Canada

Multiplication is one of the most important operations in finite field arithmetic. It is used in cryptographic and coding applications, such as elliptic curve cryptography and Reed-Solomon codes. In this paper, we consider the finite field multiplication used in elliptic curve cryptography and design concurrent error detection circuits. It is shown in the literature that the Montgomery multiplication can be used in cryptography to accelerate the scalar multiplication. Here, we use a parity-based concurrent error detection approach to increase the reliability of different Montgomery multipliers available in the literature. First, we consider bit-serial Montgomery multiplication and propose an error detection circuit. Then, we apply the same technique on the digit-serial Montgomery multiplication. Finally, we consider low time-complexity bit-parallel Montgomery multiplication and design the required components to implement the concurrent error detection circuits. ASIC implementations have been completed to analyze the time and area overheads of the proposed schemes. Also, the error detection capability is investigated by software simulations. We show that our approach results in efficient error detection schemes with small time and area overheads.

关键词： Montgomery multiplication concurrent error detection finite fields elliptic curve cryptography

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concurrent error detection in Montgomery multiplication over GF(2^m)

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2006年第2期E89A卷 566-574页

作者： Chiou, CW Lee, CY Deng, AW Lin, JM Department of Computer Science and Information Engineering Ching Yun University Taiwan Taiwan Department of Computer Information and Network Engineering Lunghwa University of Science and Technology Taiwan Taiwan Department of Information Management Ching Yun University Taiwan Taiwan Department of Information Engineering and Computer Science Feng Chia University Taiwan Taiwan Department of Computer Science and Information Engineering Taiwan Division of Continuing Education Ching Yun University Taiwan Department of Computer Information and Network Engineering Lunghwa University of Science and Technology Taiwan IEEE Taiwan Phi Tao Phi Taiwan Department of Information Management Ching Yun University Taiwan Department of Information Engineering and Computer Science Feng Chia University Taichung City Taiwan

Because fault-based attacks on cryptosystems have been proven effective, fault diagnosis and tolerance in cryptography have started a new surge of research and development activity in the field of applied cryptography. Without magnitude comparisons, the Montgomery multiplication algorithm is very attractive and popular for Elliptic Curve Cryptosystems. This paper will design a Montgomery multiplier array with a bit-parallel architecture in GF(2(m)) with concurrent error detection capability to protect it against fault-based attacks. The robust Montgomery multiplier array with concurrent error detection requires only about 0.2% extra space overhead (if m = 512 is as an example) and requires four extra clock cycles compared to the original Montgomery multiplier array without concurrent error detection.

关键词： cryptography Montgomery multiplication finite field arithmetic fault-tolerant computing concurrent error detection

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concurrent error-detection ON PROGRAMMABLE SYSTOLIC ARRAYS

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IEEE TRANSACTIONS ON COMPUTERS 1993年第6期42卷 752-756页

作者： HUGHEY, R Comput. Eng. Board of Studies California Univ. Santa Cruz CA USA Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions

This communication presents two concurrent error detection (CED) methods: skewed replicated computation streams and interleaved replicated computation streams, both well-suited for shared register and other systolic arrays. They allow software tradeoffs between time- and space-multiplexing with no special hardware. The methods can be automatically applied to any systolic program.

关键词： concurrent error detection COMPUTER ARCHITECTURE FAULT TOLERANCE LINEAR PROCESSOR ARRAY PARALLEL PROCESSING PROGRAMMABLE SYSTOLIC ARRAY SIMD BROADCAST INSTRUCTION

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concurrent error detection methods for asynchronous burst-mode machines

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IEEE TRANSACTIONS ON COMPUTERS 2007年第6期56卷 785-798页

作者： Almukhaizim, Sobeeh Makris, Yiorgos Yale Univ Dept Elect Engn New Haven CT 06520 USA Yale Univ Dept Elect Engn & Comp Sci New Haven CT 06520 USA

Asynchronous controllers exhibit various characteristics that limit the effectiveness and applicability of the concurrent error detection (CED) methods developed for their synchronous counterparts. Asynchronous Burst-Mode Machines (ABMMs), for example, do not have a global clock to synchronize the ABMM with the additional circuitry that is typically used by synchronous CED methods (for example, duplication). Therefore, performing effective CED in ABMMs requires a synchronization method that will appropriately enable the checker (for example, comparator) in order to avoid false alarms. Also, ABMMs contain redundant logic, which guarantees the hazard-free operation required for correct interaction between the circuit and its environment. Redundant logic, however, allows some single event transients to manifest themselves only as hazards but not as logic discrepancies. Therefore, performing effective CED in ABMMs requires the ability to detect hazards with which synchronous CED methods are not concerned. In this work, we first devise hardware solutions for performing checking synchronization and hazard detection. We then demonstrate how these solutions enable the development of three complete CED methods for ABMMs. The first method (Duplication-based CED) is an adaptation of the well-known duplication method within the context of ABMMs. The second method (Transition-Trigge red CED) is a variation of duplication wherein the implementation cost is reduced by allowing hazards in the duplicate circuit. In contrast to these two methods, which are nonintrusive, the third method (Berger code-based CED) is intrusive since it requires reencoding of the ABMM with check symbols based on the Berger code. Although this intrusiveness may slightly impact performance, Berger code-based CED incurs the lowest area overhead among the three methods, as indicated through experimental results.

关键词： concurrent error detection asynchronous burst-mode machines error-detecting codes Berger code

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concurrent error detection in semi-systolic dual basis multiplier over GF(2^m) using self-checking alternating logic

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IET CIRCUITS DEVICES & SYSTEMS 2010年第5期4卷 382-391页

作者： Chiou, C. W. Liang, W. -Y. Chang, H. W. Lin, J. -M. Lee, C. -Y. Ching Yun Univ Dept Comp Sci & Informat Engn Chungli 320 Taiwan Natl Taipei Univ Technol Dept Comp Sci & Informat Engn Taipei 106 Taiwan Feng Chia Univ Dept Informat Engn & Comp Sci Taichung 407 Taiwan Lunghwa Univ Sci & Technol Dept Comp Informat & Network Engn Tao Yuan 333 Taiwan

Multiplication is one of the most important finite field arithmetic operations in cryptographic computations. Recently, the attacks of fault-based cryptanalysis have been a critical threat to both symmetrical and asymmetrical cryptosystems. To prevent such kind of attacks, masking faulty signals and outputting only correct ciphers would be a feasible solution, especially suitable for finite field multiplication. Therefore a novel dual basis multiplier in GF(2(m)) with concurrent error detection capability using self-checking alternating logic is presented. The new self-checking alternating logic dual basis multiplier saves about 67% space complexity as compared with other existing dual basis multiplier with concurrent error detection capability that uses the parity checking method. The proposed dual basis multiplier takes almost as low as one extra clock cycle to achieve concurrent error detection capability. Furthermore, any existing faults in fault model are ensured to be detectable through at least one input in the authors' proposed scheme.

关键词： fault-based cryptanalysis semisystolic dual basis multiplier finite field arithmetic operation self-checking alternating logic systolic arrays digital arithmetic parity checking concurrent error detection finite field multiplication clock cycle faulty signal masking cryptographic computation asymmetrical cryptosystem fault diagnosis cryptography clocks circuit complexity Galois fields fault model multiplying circuits space complexity

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concurrent error detection in nonlinear digital circuits using time-freeze linearization

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IEEE TRANSACTIONS ON COMPUTERS 1997年第11期46卷 1208-1218页

作者： Chatterjee, A Roy, RK INTEL CORP HILLSBOROOR 97124

concurrent error detection in digital circuits is very important in applications where error in processed data can have catastrophic effects. Typically, error detection is performed by a small amount of additional hardware called the checking circuit In the past, researchers have developed techniques for concurrent error detection in linear digital state variable circuits. In this paper, we investigate concurrent error detection techniques for nonlinear digital circuits that compute polynomial functions of multiple variables. Such circuits have widespread use in the design of various classes of nonlinear digital filters. The proposed error detection schemes are possible due to the use of a new linearization method called time-freeze linearization. In this method, a nonlinear circuit is modeled as a linear circuit for each individual time frame corresponding to the time taken to process a given set of input data. The defining parameters of this linear model change from one time frame to another but are regarded as fixed or frozen in any given time frame. This allows the use of real number checksum codes for fault detection. As opposed to duplicating the entire nonlinear part of the circuit, our approach allows us to use the nonlinear functions to drive the check circuitry, while achieving full fault coverage at low hardware cost.

关键词： concurrent error detection checksum codes nonlinear digital filters self-healing systems state variable systems

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concurrent error detection in array multipliers by BIDO

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 1995年第6期142卷 425-430页

作者： Chen, TH Lee, YP Chen, LG NATL TAIWAN UNIV DEPT ELECT ENGNTAIPEI 10764TAIWAN

Array multipliers consist of full adders (FAs). When the sums and carrys are propagated down through the array, each row of FAs is used only once. Most FAs are doing no useful work at any given time. The authors design a concurrent error-detectable array multiplier using bidirectional operation (BIDO). The BIDO implementation employs the inherent idle FAs in an array multiplier to perform the repeated operation. As a result, both normal and repeated are performed in one single set of simultaneously. The experimental results show that the BIDO implementation has the following significant benefits: (i) It has a moderate hardware overhead, but little performance degradation and (ii) The time and hardware overheads are constant for detecting both single and multiple faults.

关键词： array multipliers bi-directional operation concurrent error detection fault-tolerant computing

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concurrent error detection architectures for Gaussian normal basis multiplication over GF(2^m)

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INTEGRATION-THE VLSI JOURNAL 2010年第1期43卷 113-123页

作者： Lee, Chiou-Yng Lunghwa Univ Sci & Technol Dept Comp Informat & Network Engn Taoyuan Cty 333 Taiwan

This paper presents a method of using a parity prediction scheme for detecting erroneous outputs in bit-parallel, sequential, and digit-serial Gaussian normal basis (GNB) multipliers over GF(2(m)). Although all-type NB multipliers have different time and space complexities, our analytical results indicate that all-type GNB multipliers have the same structure if they use parity prediction function. For example, in the field GF(2(233)), we have estimated that the error detection rate for a sequential multiplier is nearly 100% if a comparison is made as per clock cycle. Our analytical results also show that the area overhead of the proposed digit-serial multiplier with concurrent error detection does not exceed 5%. Several efficient parity prediction techniques will be shown in this work to provide a low overhead solution to concurrent error detection particularly when the cryptography implementations using GF(2(m)) multiplier require higher reliability and the protection against adversarial attacks. (C) 2009 Elsevier B.V. All rights reserved.

关键词： Gaussian normal basis concurrent error detection Parity prediction scheme Digit-serial multiplier

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concurrent error detection in GF(2^m) multiplication and its application in elliptic curve cryptography

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IET CIRCUITS DEVICES & SYSTEMS 2008年第3期2卷 289-297页

作者： Chelton, W. Benaissa, M. Univ Sheffield Dept Elect & Elect Engn Sheffield S1 3JD S Yorkshire England

A novel approach to achieve concurrent error detection infinite-field multiplication over GF(2(m)) that uses multiple-bit interlaced parity codes is presented. These codes are implemented as a generic parity checker, which means they can be used with any multiplier architecture. Relative to the number of parity bits used, much improved delay and error-detection performance are achieved compared to previously reported results, yet for the examples considered the area overhead did not exceed 12%. The proposed work is particularly important for cryptography implementations employing GF(2(m)) multipliers and requiring reliability and protection against adversarial attacks that use fault induction.

关键词： cryptography generic parity checker cryptography implementations concurrent error detection multiplier architecture multiple-bit interlaced parity codes error-detection performance error detection codes finite-field multiplication elliptic curve cryptography parity check codes fault induction

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