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ALMOST CERTAIN FAULT-DIAGNOSIS THROUGH ALGORITHM-BASED FAULT-TOLERANCE

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1994年第5期5卷 532-539页

作者： BLOUGH, DM PELC, A UNIV QUEBEC DEPT INFORMATHULL J8X 3X7QUEBECCANADA

Algorithm-based fault tolerance has been proposed as a technique to detect incorrect computations in multiprocessor systems. In algorithm-based fault tolerance, processors produce data elements that are checked by concurrent error detection mechanisms. In this paper, we investigate the efficacy of this approach for diagnosis of processor faults. Because checks are performed on data elements, the problem of location of data errors must first be solved. We propose a probabilistic model for the faults and errors in a multiprocessor system and use it to evaluate the probabilities of correct error location and fault diagnosis. We investigate the number of checks that are necessary to guarantee error location with high probability. We also give specific check assignments that accomplish this goal. We then consider the problem of fault diagnosis when the locations of erroneous data elements are known. Previous work on fault diagnosis required that the data sets produced by different processors be disjoint. We show, for the first time, that fault diagnosis is possible with high probability, even in systems where processors combine to produce individual data elements.

关键词： ALGORITHM-BASED FAULT TOLERANCE concurrent error detection FAULT DIAGNOSIS INTERMITTENT FAULTS PROBABILISTIC ANALYSIS

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error detection by duplicated instructions in super-scalar processors

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IEEE TRANSACTIONS ON RELIABILITY 2002年第1期51卷 63-75页

作者： Oh, N Shirvani, PP McCluskey, EJ Stanford Univ Dept Elect Engn Ctr Reliable Comp Stanford CA 94305 USA Stanford Univ Dept Comp Sci Stanford CA 94305 USA

This paper proposes a pure software technique "error detection by Duplicated Instructions" (EDDI), for detecting errors during usual system operation. Compared to other error-detection techniques that use hardware redundancy, EDDI does not require any hardware modifications to add error detection capability to the original system. EDDI duplicates instructions during compilation and uses different registers and variables for the new instructions. Especially for the fault in the code segment of memory, formulas are derived to estimate the error-detection coverage of EDDI using probabilistic methods. These formulas use statistics of the program, which are collected during compilation. EDDI was applied to eight benchmark programs and the error-detection coverage was estimated. Then, the estimates were verified by simulation, in which a fault injector forced a bit-flip in the code segment of executable machine codes. The simulation results validated the estimated fault coverage and show that approximately 1.5% of injected faults produced incorrect results in eight benchmark programs with EDDI, while on average, 20% of injected faults produced undetected incorrect results in the programs without EDDI. Based on the theoretical estimates and actual fault-injection experiments, EDDI can provide over 98% fault-coverage without any extra hardware for error detection. This pure software technique is especially useful when designers cannot change the hardware, but they need dependability in the computer system. To reduce the performance overhead, EDDI schedules the instructions that are added for detecting errors such that "Instruction-Level Parallelism" (ILP) is maximized. Performance overhead can be reduced by increasing ILP within a single super-scalar processor. The execution time overhead in a 4-way super-scalar processor is less than the execution time overhead in the processors that can issue two instructions in one cycle.

关键词： concurrent error detection error detection by duplicated instructions fault-injection experiment fault tolerance instruction-level parallelism single event upset super-scalar processor and instruction-scheduling transient fault

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DIAGNOSABILITY AND DIAGNOSIS OF ALGORITHM-BASED FAULT-TOLERANT SYSTEMS

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IEEE TRANSACTIONS ON COMPUTERS 1993年第8期42卷 924-937页

作者： VINNAKOTA, B JHA, NK PRINCETON UNIV DEPT ELECT ENGN PRINCETON NJ 08544 USA

Parallel processing architectures are now in common use for signal processing and other computation-intensive applications. These applications are characterized by high throughput and long processing periods. Such characteristics decrease the reliability of high-performance architectures. The erroneous data produced by faulty processors could have damaging consequences, particularly in critical real-time applications. It is therefore desirable that any erroneous data produced by the system be detected and located as quickly as possible. Algorithm-based fault tolerance (ABFT) is a low-cost system-level concurrent error detection and fault location scheme. We apply methods used in the analysis of multiprocessor systems employing system-level diagnosis to the analysis of ABFT systems. A new algorithm to analyze an ABFT system for its fault diagnosability is developed using these methods. Based on this work, a fault diagnosis algorithm is developed for ABFT systems. No such algorithm has been presented previously.

关键词： ALGORITHM-BASED FAULT TOLERANCE CHECKSUM ENCODING concurrent error detection concurrent FAULT DIAGNOSIS FAULT DIAGNOSABILITY

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Design and analysis of an integrated checkpointing and recovery scheme for distributed applications

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IEEE TRANSACTIONS ON KNOWLEDGE AND DATA ENGINEERING 2000年第2期12卷 174-186页

作者： Ramamurthy, B Upadhyaya, S Bhargava, B SUNY Buffalo Dept Comp Sci & Engn Buffalo NY 14260 USA Purdue Univ Dept Comp Sci W Lafayette IN 47907 USA

An integrated checkpointing and recovery scheme which exploits the low latency and high coverage characteristics of a concurrent error detection scheme is presented. Message dependency which is the main source of multistep rollback in distributed systems is minimized by using a new message validation technique derived from the notion of concurrent error detection. The concept of a new global state matrix is introduced to track error checking and message dependency in a distributed system and assist in the recovery. The analytical model, algorithms, and data structures to support an easy implementation of the new scheme are presented. The completeness and correctness of the algorithms are proved. A number of scenarios and illustrations that give the details of the analytical model are presented. The benefits of the integrated checkpointing scheme are quantified by means of simulation using an object-oriented test framework.

关键词： checkpointing concurrent error detection distributed systems message logging rollback recovery

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Approach to partially self-checking combinational circuits design

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MICROELECTRONICS JOURNAL 2004年第12期35卷 945-952页

作者： Djordjevic, GL Stojcev, MK Stankovic, TR Univ Nish Fac Elect Engn YU-18000 Nish Serbia Monteneg Serbia

This paper presents a cost-effective, non-intrusive technique of partially self-checking combinational circuits design. The proposed technique is similar to duplication with comparison, wherein duplicated function module and comparator act as a function checker that detects any erroneous response of the original function module. However, instead of realizing checker with full error-detection capability, we select a subset of erroneous responses to implement partial, but simplified function checker. A heuristic procedure that tries to find the optimal sum-of-product expression for partial function checker that minimizes its area while providing specified error coverage is described here. Effectiveness of the technique is evaluated on a set of MCNC 91 benchmark combinational circuits. (C) 2004 Elsevier Ltd. All rights reserved.

关键词： fault tolerance concurrent error detection partially self-checking circuits approximation of logic functions

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A Secure Modular Division Algorithm Embedding with error detection and Low-Area ASIC Implementation

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2020年第4期92卷 375-387页

作者： Hu, Xiaoting Qin, Zhongping Yang, Qi Huazhong Univ Sci & Technol Dept Software Engn Wuhan 430070 Hubei Peoples R China Jiangsu Normal Univ Dept Comp Sci & Technol Xuzhou 221116 Jiangsu Peoples R China Changjiang Secur Co Ltd Wuhan 430070 Hubei Peoples R China

Modular division operation has important application in public-key cryptosystems. It is the most complex and time-consumed operation in RSA and ECC. Its secure and efficient implementation greatly affects the secure and performance of these cryptosystems. In this paper, a modular division algorithm embedding with error detection is proposed. Four computing types of ASIC implementation architectures (Type-8, Type-16, Type-32, Type-64) are explored to seek the optimal tradeoff among error detection ratio, time overhead and hardware overhead. These implementation architectures are modeled in Verilog language and synthesized using Synopsys Design Compiler with OSU 90 nm CMOS standard cell library. Experiment results show that the proposed Type-64 can get almost 100% error detection probability with an average of 24.71% extra area overhead and 0.52% time overhead. In addition, for the implementation of single modular division module, the proposed Type-64 architecture saves 60.74% area overhead on average with a slight decrease of throughput rate compared with the state-of-the-art re- search. This implementation not only greatly reduces the area overhead of modular division but also improves the security of modular division implementation.

关键词： Modular division concurrent error detection Secure systolic architecture ASIC implementation

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ALGORITHM-BASED FAULT-TOLERANCE FOR FFT NETWORKS (VOL 43, PG 849, 1994)

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IEEE TRANSACTIONS ON COMPUTERS 1994年第10期43卷 1248-1248页

作者： WANG, SJ JHA, NK PRINCETON UNIV DEPT ELECT ENGNPRINCETONNJ 08544

Algorithm-based fault tolerance (ABFT) is a low-overhead system-level fault tolerance technique. Many ABFT schemes have been proposed in the past for fast Fourier transform (FFT) networks. In this paper, a new ABFT scheme for FFT networks is proposed. We show that the new approach maintains the high throughput of previous schemes, yet needs lower hardware overhead and achieves higher fault converge than previous schemes by J.Y. Jou et al. (1988) and D.I. Tao et al. (1990)

关键词： Algorithm-based fault tolerance Fast Fourier Transform concurrent error detection hardware redundancy schemes transient errors.

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PROBABILISTIC EVALUATION OF ONLINE CHECKS IN FAULT-TOLERANT MULTIPROCESSOR SYSTEMS

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IEEE TRANSACTIONS ON COMPUTERS 1992年第5期41卷 532-541页

作者： NAIR, VSS HOSKOTE, YV ABRAHAM, JA UNIV TEXAS COMP ENGN RES CTR AUSTIN TX 78758 USA

The analysis of fault-tolerant multiprocessor systems that use concurrent error detection (CED) schemes is much more difficult than the analysis of conventional fault-tolerant architectures. Various analytical techniques have been proposed to evaluate CED schemes deterministically. However, these approaches are based on worst-case assumptions related to the failure of system components. Often, the evaluation results do not reflect the actual fault tolerance capabilities of the system. In this paper, we develop a probabilistic approach to evaluate the fault detecting and locating capabilities of on-line checks in a system. The various probabilities associated with the checking schemes are identified and used in the framework of the matrix-based model [1]. Based on these probabilistic matrices, estimates for the fault tolerance capabilities of various systems are derived analytically.

关键词： ALGORITHM-BASED FAULT TOLERANCE concurrent error detection FAULT COVERAGE LOCATABILITY PROBABILISTIC TECHNIQUES

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REMOD: A new methodology for designing fault-tolerant arithmetic circuits

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1997年第1期5卷 34-56页

作者： Dutt, S Hanchek, F Dept. of Electr. Eng. Minnesota Univ. Minneapolis MN USA

REMOD (REprocessing with MicrO Delays) is a new method for fault-tolerant design of logic circuits composed of arrays of identical functional cells. The fault detection scheme is based on the principle of node covering, in which the computation of each cell is checked by a ''covering'' cell, After a faulty cell is detected, the node covering principle also allows the circuit to easily be reconfigured to perform correctly for subsequent inputs, Furthermore, the design method is extendible to multiple fault tolerance with only small increments of hardware and time. We have laid out and simulated REMOD-based circuits for adders and multipliers and show that the time overheads are a small factor of the original computation time-0 or Theta(1/n) to Theta(1/log n), far an n-cell circuit. For moderately complex cells, it is seen that area overhead is very reasonable as well.

关键词： arithmetic circuits circuit reconfiguration concurrent error detection fault diagnosis fault tolerance node-covering

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Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method

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MICROELECTRONICS RELIABILITY 2015年第3-4期55卷 696-703页

作者： An, T. Liu, K. Cai, H. Naviner, L. A. de B. Telecom Paris Tech Inst Mines Telecom CNRS LTCIUMR 5141 Paris France

Transient faults are important concerns in emerging ICs built from deep semiconductors. concurrent error detection (CED) scheme has been proved to be an efficient technique in such a context. On the other hand, the increase of multiple faults can be foreseeable in future ICs. However, reported efforts applied to quantify the efficiency of CED schemes mostly consider single faults or suppose that implemented checker mechanisms are fault-free. This paper describes an alternative analytical solution for CED circuits analysis under a more realistic hypothesis. In addition to the assumption of the whole fault-prone circuit (including checker mechanisms), different failure rates of logic gate are considered as well. The proposed approach is based on probabilistic transfer matrices and then can deal with multiple faults. The time efficiency of the proposed solution is demonstrated through arithmetic circuits. By applying this solution, classical CED schemes are discussed according to different failure rates of transistor. (C) 2015 Elsevier Ltd. All rights reserved.

关键词： concurrent error detection Multiple faults Reliability Radiation-related effects

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