Protection against transient instability and a consequent out-of-step condition is a major concern for the utility industry. An unstable system may cause serious damage to system elements such as generators and transm...
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Protection against transient instability and a consequent out-of-step condition is a major concern for the utility industry. An unstable system may cause serious damage to system elements such as generators and transmission lines, therefore out-of-step detection is essential to operate a system safely. The traditional out-of-step relays detect out-of-step conditions by using distance relays and timers. However, such a relay monitors only apparent impedance which is an indirect function of generator angle, and the relay cannot cope with the out-of-step situation for the more severe instability situation of very fast power swings which can also cause damage to transmission lines if not detected fast enough, as is the case with conventional detection techniques. Digital filters based on discrete Fourier transforms are used to calculate the frequency of a sinusoidal voltage, and then the generator angle is estimated using the deviation of the calculated frequency component of the voltage. The proposed out-of-step detection algorithm is based on the assessment of transient stability using the equal-area criterion. It is verified and tested by using ATP/EMTP MODELS, and the simulation results show that the out-of-step conditions are detected accurately employing the proposed algorithm.
Atomos is the first programming language with implicit transactions, strong atomicity, and a scalable multiprocessor implementation. Atomos is derived from Java, but replaces its synchronization and conditional waitin...
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Atomos is the first programming language with implicit transactions, strong atomicity, and a scalable multiprocessor implementation. Atomos is derived from Java, but replaces its synchronization and conditional waiting constructs with simpler transactional alternatives. The Atomos watch statement allows programmers to specify fine-grained watch sets used with the Atomos retry conditional waiting statement for efficient transactional conflict-driven wakeup even in transactional memory systems with a limited number of transactional contexts. Atomos supports open-nested transactions, which are necessary for building both scalable application programs and virtual machine implementations. The implementation of the Atomos scheduler demonstrates the use of open nesting within the virtual machine and introduces the concept of transactional memory violation handlers that allow programs to recover from data dependency violations without rolling back. Atomos programming examples are given to demonstrate the usefulness of transactional programming primitives. Atomos and Java are compared through the use of several benchmarks. The results demonstrate both the improvements in parallel programming ease and parallel program performance provided by Atomos.
A SOC-multiprocessor can achieve a high performance by using many parallel processing technologies. On a shared memory multiprocessor, synchronization and communication are performed through shared variables. In gener...
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ISBN:
(纸本)0889865078
A SOC-multiprocessor can achieve a high performance by using many parallel processing technologies. On a shared memory multiprocessor, synchronization and communication are performed through shared variables. In general, synchronization is performed apart from communication. On a SOC-multiprocessor, the TSVM cache combines communication and synchronization with the coherence maintenance among the processor cores. That is, one coherence transaction through a high-speed inter-connection on the chip realizes the communication and synchronization via a shared variable. This paper introduces the several instructions of which each instruction has the individual coherence maintenance scheme to the TSVM cache. By combining these instructions, you can realize the efficient communication, and synchronization primitives easily and systematically, which are useful in a parallel processing generally. We perform the experiments of the primitives and the applications using them on a clock-accurate simulator written in VHDL. The result shows that the TSVM cache can improve a performance of 8.5 times compared with a traditional cache memory. It is also confirmed that although the load instruction not changing the synchronization state does not achieve the best performance, it can reduce a bus traffic of 40% on an application program.
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