Current generation system-on-chips (SoCs) has been increasing in terms of complexity, resulting in dense global interconnect fabric. Routers are a critical part in neuromorphic SoC fabrics, and the majority of previou...
详细信息
ISBN:
(纸本)9781728134826
Current generation system-on-chips (SoCs) has been increasing in terms of complexity, resulting in dense global interconnect fabric. Routers are a critical part in neuromorphic SoC fabrics, and the majority of previous works do not focus on in depth verification methodology. This is despite the fact that the number of neurons in neuromorphic computing is at least 1000 times larger than conventional SoCs. Hence, it is very likely that the presented results could be affected by unit level hardware bugs that only surface during the integration phase. Additionally, some neuromorphic routers may consist of asynchronous design units, making verification even more challenging. This paper presents the verification methodology utilized to achieve high coverage in asynchronous neuromorphic routers based on the coverage driven flow, along with assertions, checkers, and scoreboarding for ensuring design correctness. The test plan was developed, beginning with random constrained tests, followed by manually designed directed tests. The combined coverage database of all the simulation runs was able to achieve up to 93% overall coverage, proving the effectiveness of the proposed verification methodology. Furthermore, the methodology was also able to detect bugs early hi the design phase, speeding up the entire design flow.
RISC-V processors based on increasingly popular open standard instruction set architecture (ISA) are challenging to verify because of their optional features, implementation flexibility, and custom extensions. However...
详细信息
ISBN:
(纸本)9789819737550;9789819737567
RISC-V processors based on increasingly popular open standard instruction set architecture (ISA) are challenging to verify because of their optional features, implementation flexibility, and custom extensions. However, their uniformity and modular design present a unique opportunity to develop a high-quality verification environment automatically. In this paper, we propose a tool named Codriver, which automatically produces a test environment for RISC-V processors using constrained random test vector generation, followed by an intelligent feedback mechanism. The results on four different RISC-V ISAs demonstrate Codriver's capabilities, effectiveness, and versatility. The feedback mechanism applies incremental patches to the test bench to fill the functional coverage gaps and achieves high coverage (similar to 99%) with a small set of instructions (similar to 300 - 400).
暂无评论