Statistical optimization algorithms must be able to optimize both mean delay and standard deviation, sigma, as they need to either improve a circuit's yield or to operate under a yield constraint. Wire delays pose...
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ISBN:
(纸本)9781612849140
Statistical optimization algorithms must be able to optimize both mean delay and standard deviation, sigma, as they need to either improve a circuit's yield or to operate under a yield constraint. Wire delays pose a significant challenge for statistical placement, as they skew signal arrival times, and thus easily affect standard deviation. This paper presents a statistical, constructive placement algorithm, SCPlace, which is based on two novel, statistical slack assignment strategies, namely MSSA (Minimum Sigma Slack Assignment) and TSZSA (Target Sigma Zero Slack Assignment). MSSA assigns wire delays on nets so as to derive a lower sigma bound for a technology-mapped, standard-cell circuit, while TSZSA assigns wire delay bounds on nets for meeting a combined (mean, sigma) constraint. Experimental results, illustrate that SCPlacer's constructivealgorithm achieves legal, routable placements, and the statistical slack assignment strategy achieves a 4.68% yield improvement average for the IWLS 2005 benchmarks over an existing commercial placement tool.
Despite the potential benefits of asynchronous circuits compared to synchronous circuits, only small advances have been made in the adaptation of asynchronous methodologies by the electronics industry. One of the most...
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ISBN:
(纸本)9780769543833
Despite the potential benefits of asynchronous circuits compared to synchronous circuits, only small advances have been made in the adaptation of asynchronous methodologies by the electronics industry. One of the most important reasons for that, is the lack of asynchronous Electronic Design Automation (EDA) tools and the fact that existing EDA tools are not suitable for asynchronous implementations. Moreover, physical EDA tools, like placementalgorithms, involve methodologies which are not applicable to asynchronous circuits, such as static timing analysis (STA) which cannot be performed in a cyclic circuit. In this work, we present CPlace, a constructive placement algorithm which can efficiently handle asynchronous circuits. We use timing separation of events for timing analysis and maintain the quasi-delay insensitive (QDI) properties by bounding the relative delays of wires in isochronic forks. We employ absolute timing constraints for performance and relative timing constraints for QDI which are handled by an ILP formulation. Experimental results show the effectiveness of CPlace in respecting QDI constraints against a synchronous, state-of-the-art industrial placer and a well-known academic placer.
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