Modern artificial intelligence systems based on neural networks need to perform a large number of repeated parallel operations quickly. Without hardware acceleration, they cannot achieve effectiveness and availability...
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Modern artificial intelligence systems based on neural networks need to perform a large number of repeated parallel operations quickly. Without hardware acceleration, they cannot achieve effectiveness and availability. Memristor-based neuromorphic computing systems are one of the promising hardware acceleration strategies. In this paper, we propose a full-size convolution algorithm (FSCA) for the memristor crossbar, which can store both the input matrix and the convolution kernel and map the convolution kernel to the entire input matrix in a full parallel method during the computation. This method dramatically increases the convolutional kernel computations in a single operation, and the number of operations no longer increases with the input matrix size. Then a bidirectional pulse control switch integrated with two extra memristors into CMOS devices is designed to effectively suppress the leakage current problem in the row and column directions of the existing memristor crossbar. The spice circuit simulation system is built to verify that the design convolutional computation algorithm can extract the feature map of the entire input matrix after only a few operations in the memristor crossbar-based computational circuit. System-level simulations based on the MNIST classification task verify that the designed algorithm and circuit can effectively implement Gabor filtering, allowing the multilayer neural network to improve the classification task recognition accuracy to 98.25% with a 26.2% reduction in network parameters. In comparison, the network can even effectively immunize various non-idealities of the memristive synaptic within 30%.
Signal processing has entered the era of big data,and improving processing efficiency becomes *** computing architectures face computational efficiency limitations due to the separation of storage and *** circuits bas...
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Signal processing has entered the era of big data,and improving processing efficiency becomes *** computing architectures face computational efficiency limitations due to the separation of storage and *** circuits based on multi-conductor devices enable full hardware convolutional neural networks(CNNs),which hold great potential to improve computational ***,when processing large-scale convolutional computations,there is still a significant amount of device redundancy,resulting in low computational power consumption and high computational ***,we innovatively propose a memristor-based in-situ convolutional strategy,which uses the dynamic changes in the conductive wire,doping area,and polarization area of memristors as the process of convolutional operations,and uses the time required for conductance switching of a single device as the computation result,embodying convolutional computation through the unique spiked digital signal of the *** strategy reasonably encodes complex analog signals into simple digital signals through a memristor,completing the convolutional computation at the device level,which is essential for complex signal processing and computational efficiency *** on the implementation of device-level convolutional computing,we have achieved feature recognition and noise filtering for braille *** believe that our successful implementation of convolutional computing at the device level will promote the construction of complex CNNs with large-scale convolutional computing capabilities,bringing innovation and development to the field of neuromorphic computing.
Presently described is a sliding-kernel computation-in-memory (SKCIM) architecture conceptually involving two overlapping layers of functional arrays, one containing memory elements and artificial synapses for neuromo...
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Presently described is a sliding-kernel computation-in-memory (SKCIM) architecture conceptually involving two overlapping layers of functional arrays, one containing memory elements and artificial synapses for neuromorphic computation, the other is used for storing and sliding convolutional kernel matrices. A low-temperature metal-oxide thin-film transistor (TFT) technology capable of monolithically integrating single-gate TFTs, dual-gate TFTs, and memory capacitors is deployed for the construction of a physical SKCIM system. Exhibiting an 88% reduction in memory access operations compared to state-of-the-art systems, a 32 x 32 SKCIM system is applied to execute common convolution tasks. A more involved demonstration is the application of a 5-layer, SKCIM-based convolutional neural network to the classification of the modified national institute of standards and technology (MNIST) dataset of handwritten numerals, achieving an accuracy rate of over 95%. The sharing of convolution kernels in convolutional operations creates a significant asymmetry between data and weight (kernel) volume. This study optimizes convolutional operations at the hardware level by utilizing threshold adjustments in dual-gate thin-film transistors (TFTs). Achieved is a reduction in memory access operations of up to 88% through data preloading and the sliding of small kernels. image
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