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Low-power and high-quality cordic-based Loeffler DCT for signal processing

IET CIRCUITS DEVICES & SYSTEMS 2007年第6期1卷 453-461页

作者： Sun, C. -C. Ruan, S. -J. Heyne, B. Goetze, J. Natl Taiwan Univ Sci & Technol Dept Elect Engn Lab Low Power Syst Taipei 106 Taiwan Univ Dortmund Informat Proc Lab D-44221 Dortmund Germany

A computationally efficient and high-quality preserving discrete cosine transform (DCT) architecture is presented. It is obtained by optimising the Loeffler DCT based on the coordinate rotation digital computer (Cordic) algorithm. The computational complexity is reduced significantly from 11 multiply and 29 add operations (Loeffler DCT) to 38 add and 16 shift operations (i.e. similar to the complexity of the binDCT) without losing quality. After synthesising with TSMC 0.13-mu m technology library, Synopsys PrimePower was used to estimate the power consumption at gate-level. The experimental results show that the proposed 8-point one-dimensional DCT architecture only consumes 19% of the area and about 16% of the power of the original Loeffler DCT. Moreover, it also retains the good transformation quality of the original Loeffler DCT. In this regard, the proposed Cordic-based Loeffler DCT is very suitable for low-power and high-quality encoder/decoders (codecs) used in battery-based systems.

关键词： signal processing discrete cosine transforms Cordic-based Loeffler DCT discrete cosine transform digital arithmetic computational complexity coordinate rotation digital computer algorithm

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algorithm for realisation, parameter analysis, and measurement of pipelined separable 3D finite impulse response filters composed of Givens rotation structures

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IET SIGNAL PROCESSING 2018年第7期12卷 857-867页

作者： Poczekajlo, Pawel Wawryn, Krzysztof Koszalin Univ Technol Fac Elect & Comp Sci PL-75453 Koszalin Poland

A novel algorithm for the realisation of an orthogonal digital system performing three-dimensional filtering for a separable transfer function is presented in this study. The algorithm is based on a state-space approach and consists of synthesis and implementation algorithms. A structure composed of Givens rotators and delay elements is obtained. A coordinate rotation digital computer algorithm has been used to implement Givens rotators in a pipelined structure. The obtained structure has been realised on a field-programmable gate array (FPGA) chip and its performance has been evaluated. It achieved good finite precision, good sensitivity of filter amplitude to filter coefficients, less noise, better impulse response, and less FPGA chip occupation. To verify the obtained results, they have been compared to the results obtained using a direct-form structure consisting of adders, multipliers, and delay elements.

关键词： FIR filters transfer functions field programmable gate arrays pipeline processing parameter analysis pipelined separable 3D finite impulse response filter Givens rotation structure orthogonal digital system three-dimensional filtering separable transfer function state-space approach coordinate rotation digital computer algorithm field-programmable gate array FPGA chip occupation

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Precomputation-based radix-4 CORDIC for approximate rotations and Hough transform

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IET CIRCUITS DEVICES & SYSTEMS 2018年第4期12卷 413-423页

作者： Parmar, Yashrajsinh Sridharan, Krishnamurthy Indian Inst Technol Madras Dept Elect Engn Madras 600036 Tamil Nadu India

Vector rotation is an important component of algorithms in digital signal processing and robotics. Often, the rotation does not require very high accuracy. This study presents a lowoverhead sign-precomputation-based architecture for approximate rotation using the coordinate rotation digital computer (CORDIC) algorithm. The proposed architecture is independent of Z-datapath, and involves precomputation of the direction of rotation for each micro-rotation angle. The approach involves selecting the optimal micro-rotation angles from a set of elementary angles in run time. Careful selection and elimination of the redundant micro-rotation angles leads to a maximum of three iterations for a majority of the input angles while also simultaneously reaching within 0:45 (of the desired rotation angle). An field programmable gate array (FPGA) implementation of the proposed rotation mode CORDIC on XC7K70T-3FBG676 Kintex-7 using Xilinx ISE 13.2 achieves roughly 50% reduction in slice-delay product and power-delay product compared to recent designs. An application of approximate rotation to Hough transform-based lane detection is presented. An efficient algorithm for generation of vote addresses in the parameter space is proposed. It is shown that accurate lane detection is possible along with resource savings using the proposed CORDIC. The proposed architecture reduces the number of additions roughly by a factor of 20 compared with the conventional method of computing a parameter for each feature point.

关键词： digital arithmetic field programmable gate arrays Hough transforms precomputation-based radix-4 CORDIC algorithm approximate rotations vector rotation image processing digital signal processing robotics low-overhead sign-precomputation-based architecture coordinate rotation digital computer algorithm Z-datapath arctangent function summation optimal microrotation angle selection elementary angles FPGA XC7K70T-3FBG676 Kintex-7 Xilinx ISE 13 2 slice-delay product reduction power-delay product reduction Hough transform-based lane detection parameter space

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Design of a unified arithmetic processor based on redundant constant-factor CORDIC with merged scaling operation

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IEE PROCEEDINGS-computerS AND digital TECHNIQUES 2000年第4期147卷 297-303页

作者： Hsiao, SF Lau, CY Natl Sun Yat Sen Univ Dept Comp Sci & Engn Taipei Taiwan

An arithmetic processor is designed based on redundant constant-factor implementation of the coordinate rotation digital computer (CORDIC) algorithm with three different modes: circular, hyperbolic and linear. Both CORDIC types (angle calculation and vector rotation) are considered in this unified processor that is capable of computing a wide variety of arithmetic and elementary functions including: multiplication, division, some common trigonometric functions, natural logarithms. square roots, vector norm and phase. Furthermore, by merging the scaling operation with the regular CORDIC iterations, the processor based on folded (iterative) CORDIC architecture reduces by about 1/4 the total number of iterations in one complete CORDIC operation.

关键词： signal processing square roots redundant constant-factor CORDIC natural logarithms vector norm vector rotation digital arithmetic methods angle calculation trigonometric functions digital signal processing coordinate rotation digital computer algorithm digital arithmetic merged scaling operation redundant constant-factor implementation unified arithmetic processor

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Improved VLSI architecture for triangular windowed sliding DFT based on CORDIC algorithm

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IET CIRCUITS DEVICES & SYSTEMS 2019年第2期13卷 251-258页

作者： Kulshreshtha, Tanmai Dhar, Anindya Sundar Indian Inst Technol Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

This study presents a very-large-scale integration (VLSI) architecture for the triangular windowed sliding discrete Fourier transform (SDFT) based on coordinate rotation digital computer (CORDIC) algorithm. In the literature, the triangular windowed SDFT is obtained by direct cascading of two SDFT modules, whereas the idea of direct cascading leads to the error in the odd bins of the spectrum. The proposed architecture is modified to provide the correct outputs with a high-throughput rate compared to the existing designs. The SDFT has a recursive structure, and therefore it accumulates the error over iterations as the computation proceeds. A refreshing mechanism is utilised to limit the inaccuracy at the final output. The concept of generalised architecture as an area efficient implementation for obtaining more number of discrete Fourier transform (DFT) bins is introduced. An architecture is implemented using Verilog HDL on FPGA as well as in ASIC platform, and its arithmetic verification is performed in MATLAB.

关键词： field programmable gate arrays discrete Fourier transforms VLSI hardware description languages digital arithmetic signal processing application specific integrated circuits VLSI architecture triangular windowed CORDIC algorithm very-large-scale integration architecture discrete Fourier coordinate rotation digital computer algorithm direct cascading SDFT modules odd bins correct outputs high-throughput rate computation proceeds final output generalised architecture (DFT) bins

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Optimised CORDIC-based atan2 computation for FPGA implementations

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ELECTRONICS LETTERS 2017年第19期53卷 1296-1298页

作者： Torres, V. Valls, J. Canet, M. J. Univ Politecn Valencia Inst Telecomunicac & Aplicac Multimedia Valencia Spain

A method for the implementation of the atan2 operator based on the coordinate rotation digital computer algorithm is described. In the proposal, the computation of the z-path takes advantage of the look-up table-based FPGA resources to reduce by between 17 and 25%, without performance deterioration, the overall area of the unrolled architecture.

关键词： field programmable gate arrays digital arithmetic table lookup optimised CORDIC-based atan2 computation atan2 operator coordinate rotation digital computer algorithm z-path computation look-up table-based FPGA resources

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