Current generation system-on-chips (SoCs) has been increasing in terms of complexity, resulting in dense global interconnect fabric. Routers are a critical part in neuromorphic SoC fabrics, and the majority of previou...
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ISBN:
(纸本)9781728134826
Current generation system-on-chips (SoCs) has been increasing in terms of complexity, resulting in dense global interconnect fabric. Routers are a critical part in neuromorphic SoC fabrics, and the majority of previous works do not focus on in depth verification methodology. This is despite the fact that the number of neurons in neuromorphic computing is at least 1000 times larger than conventional SoCs. Hence, it is very likely that the presented results could be affected by unit level hardware bugs that only surface during the integration phase. Additionally, some neuromorphic routers may consist of asynchronous design units, making verification even more challenging. This paper presents the verification methodology utilized to achieve high coverage in asynchronous neuromorphic routers based on the coveragedriven flow, along with assertions, checkers, and scoreboarding for ensuring design correctness. The test plan was developed, beginning with random constrained tests, followed by manually designed directed tests. The combined coverage database of all the simulation runs was able to achieve up to 93% overall coverage, proving the effectiveness of the proposed verification methodology. Furthermore, the methodology was also able to detect bugs early hi the design phase, speeding up the entire design flow.
The constant pressure for making functional verification more agile has led to the conception of coverage driven verification (CDV) techniques. CDV has been implemented in verification testbenches using supervised lea...
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The constant pressure for making functional verification more agile has led to the conception of coverage driven verification (CDV) techniques. CDV has been implemented in verification testbenches using supervised learning techniques to model the relationship between coverage events and stimuli generation, providing a feedback between them. One commonly used technique is the classification- or decision-tree data mining, which has shown to be appropriate due to the easy modeling. Learning techniques are applied in two steps: training and application. Training is made on one or more sets of examples, which relate datasets to pre-determined classes. Precision of results by applying the predictive learning concept has shown to be sensitive to the size of the training set and the amount of imbalance of associated classes, this last meaning the number of datasets associated to each class is very different from each other. This work presents experiments on the manipulation of data mining training sets, by changing the size and reducing the imbalances, in order to check their influence on the CDV efficiency. To do that, a circuit example with a large input space and strong class imbalance was selected from the application domain of multimedia systems and another one, with a small input space that affects the coverage occurrences, was selected from the communication area.
This work presents the application of a mixed strategy that combines Constrained Random Tests (CRT) and coverage driven verification (CDV) as well as the development of a coverage model for Floating Point Unit (FPU) d...
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ISBN:
(纸本)9781479968480
This work presents the application of a mixed strategy that combines Constrained Random Tests (CRT) and coverage driven verification (CDV) as well as the development of a coverage model for Floating Point Unit (FPU) designs. The proposed strategy is materialized in two key verification components for functional verification: an input generator and a verification monitor. The generator module creates random input operands based on constraints for each operation. The monitor component not only checks the result but also indicates which cases have not been tested and estimates how much of the design functionality has been tested. Tests show that using CRT-only strategy the functional does not reach the complete coverage. However, using the proposed coverage driven verification approach not only reaches 100% coverage but also speeds up the verification up to 4.5x.
verification architects need to make use of randomness supported by System Verilog and be able to define a generic path for the test to follow. This path represents a subset of features, and allows the test to randoml...
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ISBN:
(纸本)9781467399944
verification architects need to make use of randomness supported by System Verilog and be able to define a generic path for the test to follow. This path represents a subset of features, and allows the test to randomly explore the design space to explore corners in depth. Setting up a test case for such designs requires a well-defined stimulus generation methodology. Off-the-shelf scenario libraries and a synchronization and scheduling process methodology for the parallel stimuli need to be reused across several test cases. In this paper, we define a methodology for creating test scenarios and making use of object oriented principles to build composite layered scenario sequences with a generic parallel stimuli synchronization process. We built our methodology as a generic library code to be reused in many designs. A recent memory controller design is used to demonstrate our methodology. The results of applying this methodology on test cases show enhancements on coverage closure and performance.
The Usage of Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASICs) with complex functionalities such as Digital Signal Processing (DSP) is increasing in onboard space applications....
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ISBN:
(纸本)9781509000333
The Usage of Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASICs) with complex functionalities such as Digital Signal Processing (DSP) is increasing in onboard space applications. verification of these complex designs within limited schedule and resources is challenging. In order to ensure reliable functioning of these designs in all possible run time conditions, functional verification is required to be carried out thoroughly. Development of an automated self-checking verification environment or test benches, including generation of bit-accurate golden reference values, is complex and time consuming task even with the use of state-of-the-art Hardware verification Languages (HVLs) and methodology such as System-Verilog (SV) and Universal verification Methodology (UVM) respectively. This paper discusses a method for functional verification of DSP based VLSI design using SV and Matlab. The architecture of verification environment and technique for coupling of Matlab with SV based verification environment and generation of bit-accurate golden references, in real time is also discussed in detail, along with two case studies.
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