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6th IEEE International Conference on Software Testing, Verification and Validation (ICST)

作者： Czerwonka, Jacek Microsoft Res Redmond WA USA

ISBN: (纸本)9780769549934;9781479913244

Combinatorial test suite design is a test generation technique, popular in part due to its ability to achieve coverage and defect finding power approximating that of exhaustive testing while keeping test suite sizes constrained. In recent years, there have been numerous advances in combinatorial test design techniques, in terms of efficiency and usability of methods used to create them as well as in understanding of their benefits and limitations when applied to real world software. Numerous case studies have appeared presenting practical applications of the combinatorial test suite design techniques, often comparing them with manually-created, random, or exhaustive suites. These comparisons are done either in terms of defects found or by applying some code coverage metric. Since many different and valid combinatorial test suites of strength t can be created for a given test domain, the question whether they all have the same coverage properties is a pertinent one. In this paper we explore the stability of size and coverage of combinatorial test suites. We find that in general coverage levels increase and coverage variability decreases with increasing order of combinations t;however we also find exceptions with implications for practitioners. In addition, we explore cases where coverage achieved by combinatorial test suites of order t applied to the same program is not different from test suites of order t-1. Lastly, we discuss these findings in context of the ongoing practice of applying code coverage metrics to measure effectiveness of combinatorial test suites.

关键词： Pairwise testing combinatorial testing test case generation test case design coverage metrics statement and branch coverage

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Improving Fuzzing through Controlled Compilation 5

Improving Fuzzing through Controlled Compilation

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5th IEEE European Symposium on Security and Privacy (IEEE Euro S and P)

作者： Simon, Laurent Verma, Akash Samsung Res Amer Mountain View CA 94043 USA

ISBN: (纸本)9781728150871

We observe that operations performed by standard compilers harm fuzzing because the optimizations and the Intermediate Representation (IR) lead to transformations that improve execution speed at the expense of fuzzing. To remedy this problem, we propose 'controlled compilation', a set of techniques to automatically re-factor a program's source code and cherry pick beneficial compiler optimizations to improve fuzzing. We design, implement and evaluate controlled compilation by building a new toolchain with Clang/LLVM. We perform an evaluation on 10 open source projects and compare the results of AFL to state-of-the-art grey-box fuzzers and concolic fuzzers. We show that when programs are compiled with this new toolchain, AFL covers 30% new code on average and finds 21 additional bugs in real world programs. Our study reveals that controlled compilation often covers more code and finds more bugs than state-of-the-art fuzzing techniques, without the need to write a fuzzer from scratch or resort to advanced techniques. We identify two main reasons to explain why. First, it has proven difficult for researchers to appropriately configure existing fuzzers such as AFL. To address this problem, we provide guidelines and new LLVM passes to help automate AFL's configuration. This will enable researchers to perform a fairer comparison with AFL. Second, we find that current coverage-based evaluation measures (e.g. the total number of visited lines, edges or BBs) are inadequate because they lose valuable information such as which parts of a program a fuzzer actually visits and how consistently it does so. coverage is considered a useful metric to evaluate a fuzzer's performance and devise a fuzzing strategy. However, the lack of a standard methodology for evaluating coverage remains a problem. To address this, we propose a rigorous evaluation methodology based on 'qualitative coverage'. Qualitative coverage uniquely identifies each program line to help understand which lines are

关键词： afl controlled compilation coverage coverage mesaures coverage metrics Fuzzing fuzzing consistency fuzzing strategy llvm qualitative coverage

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Exploring the Mysteries of System-Level Test 29

Exploring the Mysteries of System-Level Test

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29th IEEE Asian Test Symposium (ATS)

作者： Polian, Ilia Anders, Jens Becker, Steffen Bernardi, Paolo Chakrabarty, Krishnendu ElHamawy, Nourhan Sauer, Matthias Singh, Adit Reorda, Matteo Sonza Wagner, Stefan Univ Stuttgart Inst Comp Engn & Comp Architecture Stuttgart Germany Univ Stuttgart Inst Smart Sensors Stuttgart Germany Univ Stuttgart Inst Software Engn Stuttgart Germany Politecn Torino Dept Control & Comp Engn Turin Italy Duke Univ Dept Elect & Comp Engn Durham NC USA Advantest Europe Boblingen Germany Auburn Univ Dept Elect & Comp Engn Auburn AL 36849 USA

ISBN: (纸本)9781728174679

System-level test, or SLT, is an increasingly important process step in today's integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge about what SLT is precisely and why it is used despite its considerable costs and complexities. We discuss the types or failures covered by SLT, and outline approaches to quality assessment, test generation and root-cause diagnosis in the context of SLT. Observing that the theoretical understanding for all these questions has not yet reached the level of maturity of the more conventional structural and functional test methods, we outline new and promising directions for methodical developments leveraging on recent findings from software engineering.

关键词： System-level test coverage metrics diagnosis

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Minotaur: Adapting Software Testing Techniques for Hardware Errors 19

Minotaur: Adapting Software Testing Techniques for Hardware ...

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24th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Mahmoud, Abdulrahman Venkatagiri, Radha Ahmed, Khalique Misailovic, Sasa Marinov, Darko Fletcher, Christopher W. Adve, Sarita, V Univ Illinois Champaign IL 61820 USA

ISBN: (纸本)9781450362405

With the end of conventional CMOS scaling, efficient resiliency solutions are needed to address the increased likelihood of hardware errors. Silent data corruptions (SDCs) are especially harmful because they can create unacceptable output without the user's knowledge. Several resiliency analysis techniques have been proposed to identify SDC-causing instructions, but they remain too slow for practical use and/or sacrifice accuracy to improve analysis speed. We develop Minotaur, a novel toolkit to improve the speed and accuracy of resiliency analysis. The key insight behind Minotaur is that modern resiliency analysis has many conceptual similarities to software testing;therefore, adapting techniques from the rich software testing literature can lead to principled and significant improvements in resiliency analysis. Minotaur identifies and adapts four concepts from software testing: 1) it introduces the concept of input quality criteria for resiliency analysis and identifies PC coverage as a simple but effective criterion;2) it creates (fast) minimized inputs from (slow) standard benchmark inputs, using the input quality criteria to assess the goodness of the created input;3) it adapts the concept of test case prioritization to prioritize error injections and invoke early termination for a given instruction to speed up error-injection campaigns;and 4) it further adapts test case or input prioritization to accelerate SDC discovery across multiple inputs. We evaluate Minotaur by applying it to Approxilyzer, a state-of-the-art resiliency analysis tool. Minotaur's first three techniques speed up Approxilyzer's resiliency analysis by 10.3X (on average) for the workloads studied. Moreover, they identify 96% (on average) of all SDC-causing instructions explored, compared to 64% identified by Approxilyzer alone. Minotaur's fourth technique (input prioritization) enables identifying all SDC-causing instructions explored across multiple inputs at a speed 2.3X faster (on average)

关键词： Hardware reliability Resiliency analysis Silent data corruption (SDC) Fault tolerance Software testing coverage metrics Input minimization and prioritization

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Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2018年第6期26卷 1026-1039页

作者： Bhowmik, Biswajit Biswas, Santosh Deka, Jatindra Kumar Bhattacharya, Bhargab B. IIT Guwahati Dept Comp Sci & Engn Gauhati 781039 India Indian Stat Inst Kolkata Adv Comp & Microelect Unit Kolkata 700108 India

With the advent of rapidly evolving nanoelectronic systems, compact implementation of versatile and dense network-on-chips (NoCs) on a die has emerged as technology-of-choice for multicore computing. However, because of the increased density, NoCs often suffer from various types of manufacturing faults, which degrade the yield and jeopardize the reliability of the overall system. For example, short-channel faults in an NoC often cause system-level failures that may have significant impact on its performance. This paper proposes a cluster-based distributed scheme for online testing of short faults in NoC channels. The proposed algorithm detects both intra and interchannel short faults and identifies the underlying faulty channel-wires connected to a node. The nodes in a cluster-set are appropriately scheduled to reduce test time. The approach scales to larger NoCs irrespective of size of the network and channel width. The proposed scheme also extends its application from regular to irregular NoCs, and to other channel faults like open. Fault simulation shows that the proposed cluster-driven scheme is capable of detecting all modeled short-channel faults. Online evaluation of the scheme also reveals the extent of impact that the short faults impart on various performance metrics for large traffic. Compared to prior work, it reduces hardware area overhead up to 27% and test time by more than 21x on several test cases. In addition, packet latency and energy consumption are reduced by 19.47%-40.16% and 17.57%-34.20%, respectively.

关键词： coverage metrics fault modeling and testing intra and interchannel shorts network-on-chip (NoC) performance metrics system-level failures

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Improving the efficiency of functional verification based on test prioritization

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MICROPROCESSORS AND MICROSYSTEMS 2016年第Mar.期41卷 1-11页

作者： Wang, Shupeng Huang, Kai Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310027 Zhejiang Peoples R China

Functional verification has become the key bottleneck that delays time-to-market during the embedded system design process. And simulation-based verification is the mainstream practice in functional verification due to its flexibility and scalability. In practice, the success of the simulation-based verification highly depends on the quality of functional tests in use which is usually evaluated by coverage metrics. Since test prioritization can provide a way to Simulate the more important tests which can improve the coverage metrics evidently earlier, we propose a test prioritization approach based on the clustering algorithm to obtain a high coverage level earlier in the simulation process. The k-means algorithm, which is one of the most popular clustering algorithms and usually used for the test prioritization, has some shortcomings which have an effect on the effectiveness of test prioritization. Thus we propose three enhanced k-means algorithms to overcome these shortcomings and improve the effectiveness of the test prioritization. Then the functional tests in the simulation environment can be ordered with the test prioritization based on the enhanced k-means algorithms. Finally, the more important tests, which can improve the coverage metrics evidently, can be selected and simulated early within the limited simulation time. Experimental results show that the enhanced k-means algorithms are more accurate and efficient than the standard k-means algorithm for the test prioritization, especially the third enhanced k-means algorithm. In comparison with simulating all the tests randomly, the more important tests, which are selected with the test prioritization based on the third enhanced k-means algorithm, achieve almost the same coverage metrics in a shorter time, which achieves a 90% simulation time saving. (C) 2015 Elsevier B.V. All rights reserved.

关键词： Functional verification Simulation-based verification coverage metrics Test prioritization k-means algorithm

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Towards a Scalable Test Solution for the Analysis of Interconnect Shorts in on-Chip Networks 24

Towards a Scalable Test Solution for the Analysis of Interco...

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24th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)

作者： Bhowmik, Biswajit Deka, Jatindra Kumar Biswas, Santosh Indian Inst Technol Guwahati Dept Comp Sci & Engn Gauhati India

ISBN: (纸本)9781509034321

Traditional bus-based systems-on-chip (SoCs) are turned to on-chip networks (NoCs) to overcome communication bottleneck. But, fabricating such NoC-based systems without any defect in interconnects or logics is a major challenge. This paper proposes a cost effective and scalable on-line test solution that detects and diagnoses intra-and inter-shorts in NoC interconnects. The proposed solution offers constant test time with general NoC topologies, and channel widths considering little hardware area and performance overheads. Simulation results establish the effectiveness of the proposed solution. We see that the test time is reduced by 0.5-11.25x achieving 100% coverage metrics. Simulation results also reveal the significant effect of interconnect shorts on network performance at large traffics. We see that our test solution improves packet latency by 14.98-40.57% and reduces energy consumption of a packet flit by 6.83-31.19%.

关键词： interconnect shorts odd-even node system level failures fault detection fault diagnosis coverage metrics performance metrics

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A Topology-Agnostic Test Model for Link Shorts in On-Chip Networks

A Topology-Agnostic Test Model for Link Shorts in On-Chip Ne...

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IEEE International Conference on Systems, Man, and Cybernetics (SMC)

作者： Bhowmik, Biswajit Deka, Jatindra Kumar Biswas, Santosh Bhattacharya, Bhargab B. Indian Inst Technol Dept Comp Sci & Engn Gauhati India Indian Stat Inst Adv Comp & Microelect Unit Kolkata India

ISBN: (纸本)9781509018970

With the ever-shrinking global geometries on a die and the concomitant rise in the complexity of interconnections in an on-chip network (NoC), the links used therein often suffer from various manufacturing defects such as shorts. These defects not only cause logical or functional errors but also give rise to various other system level failures such as duplication, misrouting, or dropping of a packet, thereby impacting the performance of the network significantly. This paper proposes an on-line test method that detects the presence of pairwise-shorts, if any, and identifies the faulty links. Several performance metrics are evaluated to demonstrate the impact of these faults, and simulation results demonstrate 100% coverage. The proposed method scales well to large-size NoCs irrespective of the topology and link-width.

关键词： pairwise shorts diagonal router fault detection fault diagnosis coverage metrics performance metrics

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Impact of NoC Interconnect Shorts on Performance metrics 22

Impact of NoC Interconnect Shorts on Performance Metrics

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22nd National Conference on Communications (NCC)

作者： Bhowmik, Biswajit Biswas, Santosh Deka, Jatindra Kumar Indian Inst Technol Guwahati Dept Comp Sci & Engn Gauhati India

ISBN: (纸本)9781509023615

Duplication, misrouting, and dropping of packets due to short faults on network-on-chip (NoC) interconnects have become a burden and significant impact on performance metrics. This paper proposes an adaptive approach that detects and locates intra-channel short faults on NoC interconnects, and accounts impact of the faults on performance metrics. The model is scalable with all NoCs. Simulations show the effectiveness of proposed approach and measure different performance metrics with faulty channels on various NoCs.

关键词： interconnect shorts packet overloading packet misrouting packet timeout fault detection fault diagnosis coverage metrics performance metrics

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Unified coverage Methodology for SoC Post-Silicon Validation

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Optics and Photonics Journal 2016年第10期6卷 261-268页

作者： Semih Aslan G. Karuna Ranganathapura Chandrai Vittal Siddaiah Ingram School of Engineering Electrical Engineering Texas State University San Marcos TX USA Intel Corporation Austin TX USA

The System-on-Chip’s increased complexity and shortened design cycle calls for innovation in design and validation. A high quality System-on-Chip creates distinction and position in the market, and validation is the key to a quality product. Validation consumes >60% of the product cycle. Therefore, validation should be carried out efficiently. Validation must be quantified to aid in determining its quality. Pre-silicon uses various coverage metrics for quantifying the validation. The available on-chip coverage logic limits the use of pre-silicon-like coverage metrics in post-silicon. Although on-chip coverage logic increases observability, it does not contribute to the functional logic;hence, they are controlled and limited. Discounting the need for the on-chip coverage logic, the question to be answered is whether or not these pre-silic-on coverage metrics applicable to post-silicon. We discuss the reasons for limited applicability of pre-silicon coverage metrics in post-silicon. This paper presents a unified SoC post-silicon coverage methodology centered on functional coverage metrics.

关键词： SoC IoT coverage metrics Post-Silicon

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