检索结果-内蒙古大学图书馆

What causes a system to satisfy a specification?

ACM TRANSACTIONS ON COMPUTATIONAL LOGIC 2008年第3期9卷 159-184页

作者： Chockler, Hana Halpern, Joseph Y. Kupferman, Orna Univ Haifa IL-31905 Haifa Israel Cornell Univ Dept Comp Sci Ithaca NY 14853 USA Hebrew Univ Jerusalem Sch Engn & Comp Sci IL-91904 Jerusalem Israel

Even when a system is proven to be correct with respect to a specification, there is still a question of how complete the specification is, and whether it really covers all the behaviors of the system. coverage metrics attempt to check which parts of a system are actually relevant for the verification process to succeed. Recent work on coverage in model checking suggests several coverage metrics and algorithms for finding parts of the system that are not covered by the specification. The work has already proven to be effective in practice, detecting design errors that escape early verification efforts in industrial settings. In this article, we relate a formal definition of causality given by Halpern and Pearl to coverage. We show that it gives significant insight into unresolved issues regarding the definition of coverage and leads to potentially useful extensions of coverage. In particular, we introduce the notion of responsibility, which assigns to components of a system a quantitative measure of their relevance to the satisfaction of the specification.

关键词： algorithms theory verification model checking causality responsibility coverage metrics

来源：评论

学校读者我要写书评

暂无评论

Graph based test case generation for TLM functional verification

引用

MICROPROCESSORS AND MICROSYSTEMS 2008年第5-6期32卷 288-295页

作者： Kakoee, Mohammad Reza Neishaburi, M. H. Mohammadi, Siamak Univ Tehran Sch Elect & Comp Engn Nanoelect Ctr Excellence Tehran 14174 Iran

Describing complex systems at a high level of abstraction provides designers with the possibility of exploring multiple SoC design architectures before committing to the low level-details of a complete implementation. Transaction level modeling understandably expedites the design simulation and verification. During the verification process, generating good test cases plays a significant role in determining the quality of the design. Inadequate test cases May Cause bugs to remain. In this paper, first, in order to generate test cases for a TL model, we present a Control-Transaction Graph (CTG) which describes the behavior of a TL Model. A Control Graph is a control flow graph of a module in the design and transactions represent the interactions such as synchronization between modules. Second, we define dependent paths (DePaths) on the CTG as test cases for a transaction level model, which can find communication errors in Simulation. We also give coverage metrics for a TL model to measure the quality of the generated test cases. Finally, we apply our method on the SystemC model of AMBA-AHB bus and JPEG encoder and generate test cases based on the CTG of these models. Crown Copyright (C) 2008 Published by Elsevier B.V. All rights reserved.

关键词： TLM functional test case generation SystemC verification coverage metrics

来源：评论

学校读者我要写书评

暂无评论

Functional test-case generation by a control transaction graph for TLM verification

Functional test-case generation by a control transaction gra...

引用

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools

作者： Kakoee, Mohammad Reza Neishaburi, M. H. Mohanimadi, Siamak Azad Univ Damavand Branch Tehran Iran

ISBN: (纸本)9780769529783

Transaction level modeling allows exploring several SoC design architectures leading to better performance and easier verification of the final product. Test cases play an important role in determining the quality of a design. Inadequate test-cases may cause bugs to remain after verification. Although TLM expedites the verification of a hardware design, the problem of having high coverage test cases remains unsettled at this level of abstraction. In this paper, first, in order to generate test-cases for a TL model we present a Control-Transaction Graph (CTG) describing the behavior of a TL Model. A Control Graph is a control flow graph of a module in the design and Transactions represent the interactions such as synchronization between the modules. Second, we define dependent paths (DePaths) on the CTG as test-cases for a transaction level model. The generated DePaths can find some communication errors in simulation and detect unreachable statements concerning interactions. We also give coverage metrics for a TL model to measure the quality of the generated test-cases. Finally, we apply our method on the SystemC model of AMBA-AHB bus as a case study and generate test-cases based on the CTG of this model.

关键词： TLM test case generation verification coverage metrics

来源：评论

学校读者我要写书评

暂无评论

Observability statement coverage based on dynamic factored use-definition chains for functional verification

引用

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2006年第3期22卷 273-285页

作者： Lv, Tao Fan, Jian-Ping Li, Xiao-Wei Liu, Ling-Yi Chinese Acad Sci Inst Comp Technol Key Lab Comp Syst & Architecture Adv Test Technol Lab Beijing Peoples R China

Simulation is still the primary verification method for integrated circuit designs, and coverage evaluation is indispensable for it on account of its incompleteness. As the functional complexity of modern designs is increasing dramatically, it is necessary to take observability into consideration for coverage metrics. In this paper we extend factored use-definition chains (FUD chains), a mature data structure in compilers, from sequential software to concurrent hardware design, and propose dynamic FUD chains (DFUD chains). Based on it, we present an observability model and an algorithm to evaluate observability-based statement coverage. This technique has several advantages. Firstly, it could be easily integrated into compilers or simulators for hardware description languages, since it utilizes many flow analysis techniques adopted in compilers. Secondly, it can be combined with many controllability metrics, such as statement coverage metric, since the observability model is based on definitions and uses of variables. The proposed technique has been implemented as a prototype tool for Verilog designs, and experimental results show its benefits.

关键词： design verification coverage metrics observability dynamic factored use-definition chains data-flow analysis

来源：评论

学校读者我要写书评

暂无评论

Observability statement coverage based on dynamic factored use-definition chains for functional verification

Observability statement coverage based on dynamic factored u...

引用

9th IEEE European Test Symposium (ETS 2004)

作者： Lv, Tao Fan, Jian-Ping Li, Xiao-Wei Liu, Ling-Yi Chinese Acad Sci Inst Comp Technol Key Lab Comp Syst & Architecture Adv Test Technol Lab Beijing Peoples R China

关键词： design verification coverage metrics observability dynamic factored use-definition chains data-flow analysis

来源：评论

学校读者我要写书评

暂无评论

Reusable-On-Chip system level verification for simulation emulation and silicon

Reusable-On-Chip system level verification for simulation em...

引用

11th Annual IEEE International Workshop on High Level Design Validation and Test

作者： Maman, Avishay Goldschlager, Sharon Miller, Hillel Bell, David Slater, Rob Ben-Moshe, Oded Levi, Nissan Gilboa, Hagit Freescale Semicond Israel Shenkar 1 IL-46120 Herzliyya Israel

ISBN: (纸本)142440679X

Absolute verification of System On Chip (SoC) has become infeasible due to the huge number of chip-level scenarios to cover. System level verification validates the integration of independently-verified components such as cores, peripherals, caches and memories. Some of the most elusive system level bugs can only be detected by scenarios that exercise several components, each in a different configuration. This paper presents a methodology for SoC System level verification, comprised of high level software that simultaneously exercises multiple hardware components. It consists of a fight operating system which schedules threads for non-preemptive interleaved runs. Each thread complies with a uniform structure, and activates a specific functionality of the system. The interaction of multiple threads allows for realistic scenarios, testing bus traffic stress, multiplexing, and state machines, reaching unanticipated corner-cases. The OS includes a run time constraint solver for randomly selecting parameters for peripheral configuration. Similar capabilities require dedicated testbenches such as Vera or e which lack compilers and thus cannot be applied to silicon. The described framework is not dependent on a specific tool, but based on C, therefore compiled to chip. Reusability over project fife-cycle is achieved by having the same test-cases run on simulation, emulation and silicon, allowing comparison of test results. A simulation speed-up of over 100X is achieved, by replacing RTL core with stub, compiling application code to the host machine, and using an API for the interaction of the design and application. This methodology was applied to the New Quad-Core MSC8144 supporting a very high I/O bandwidth and providing an optimal DSP solution for wireline/wireless infrastructure applications. The same methodology was used in simulation, emulation and silicon modes. It led to high coverage of system level scenarios, and discovery of system level bugs which could have ta

关键词： SoC verification testbench coverage metrics Emulation Silicon debug

来源：评论

学校读者我要写书评

暂无评论

An Efficient Evaluation and Vector Generation Method for Observability-Enhanced Statement coverage

引用

Journal of Computer Science & Technology 2005年第6期20卷 875-884页

作者：鲁巍杨修涛吕涛李晓维 Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 P.R. China Graduate School of the Chinese Academy of Sciences Beijing 100039 P.R. China School of Computer and Information Hefei University of Technology Hefei 230009 P.R. China

coverage evaluation is indispensable for verification via simulation. As the functional complexity of modern design is increasing at a breathtaking pace, it is requisite to take observability into account. Unfortunately, nowadays coverage metrics taking observability into account are not very satisfactory. On the one hand, for the observability assessment algorithms proposed up to now, the overhead of computing is large, so they could not be integrated into simulation tools easily. On the other hand, the vector generation methods involving the metrics taking observability into account are not very efficient, and there exists a disconnection between these metrics and the vector generation process. In this paper, some original ideas for the problems above are presented. （1） Precise and concise abstract representations from HDL （Hardware Description Language） descriptions at RTL （Register Transfer Level） are presented to model observability information. （2） A novel observability evaluation method based on the proposed models is introduced. This method is more computationally efficient than prior efforts to assess observability and it could be integrated into compilers and simulators easily. （3） A new simulation vector generation procedure involving the observability-enhanced statement coverage metric is developed. The method is simulation：based and driven by the distribution of unobserved statements. During this procedure, the proposed algorithm always tries to cover all unobserved statements, and reduce unnecessary backtracking, so it is efficient. The methods proposed have been implemented as a prototype tool for VHDL designs, and the results on benchmarks show significant benefits.

关键词： design verification simulation coverage metrics observability vector generation

来源：评论

学校读者我要写书评

暂无评论

On automatic generation of RTL validation test benches using circuit testing techniques 03

On automatic generation of RTL validation test benches using...

引用

Proceedings of the 13th ACM Great Lakes symposium on VLSI

作者： Indradeep Ghosh Srivaths Ravi Fujitsu Laboratories of America Sunnyvale CA NEC Laboratories America Princeton NJ

In this paper, we examine how good validation test benches can be automatically generated starting from the RTL description of a circuit. We develop our methodology based on extensive experiments performed with severa... 详细信息

ISBN: (纸本)9781581136777

关键词： coverage metrics RTL testing test test sets branch coverage universal test sets fault coverage path coverage OCCOM toggle coverage RTL ATPG design validation small validation testing generation ATPG testbench code coverage

来源：评论

学校读者我要写书评

暂无评论

A biased random instruction generation environment for architectural verification of pipelined processors

引用

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2000年第1-2期16卷 13-27页

作者： Chang, TC Iyengar, V Rudnick, EM Compaq Comp Corp Shrewsbury MA 01545 USA Univ Illinois Ctr Reliable & High Performance Comp Dept Elect & Comp Engn Urbana IL 61801 USA

Architectural verification is a critical aspect of the microprocessor design cycle. In this paper, we present a design verification environment centered around a biased random instruction generator for simulation-based architectural verification of pipelined microprocessors. The instruction generator uses biases specified by the user to generate instruction sequences for simulation. These biases are not hard-coded and can thus be changed depending on the specific areas in the design and type of design errors being targeted. Correctness checking is achieved using assertion checking and end-of-state comparison with a high-level architectural model. Several architectural-level errors are introduced into a behavioral model of the DLX processor to investigate the processor's response in the presence of design errors. Simulation experiments conducted using the behavioral model show that biased random instruction sequences provide higher coverage of RTL conditional branches and design errors than random instruction sequences or manually-generated test programs. Furthermore, instruction sequences containing a high percentage of read-after-write (RAW) and control dependencies are the most useful.

关键词： architectural verification biased random instruction generation correctness checking coverage metrics design error coverage design verification

来源：评论

学校读者我要写书评

暂无评论

Software coverage metrics and Operational Reliability

引用

IFAC Proceedings Volumes 1990年第6期23卷 67-69页

作者： A. Veevers Department of Statistics and Computational Mathematics university of Liverpool P.D. Box 147 Liverpool UK

A relationship between operational reliability growth and coverage is described. A simple method of fitting the relation is illustrated using an example. The coverage metrics TER 1 , TER 2 and TER 3 are used and their... 详细信息

关键词： Reliability coverage metrics program testing software engineering

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：