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Applying an SMT Solver to coverage-driven Design verification

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2018年第7期E101A卷 1053-1056页

作者： Hamaguchi, Kiyoharu Shimane Univ Dept Math & Comp Sci Matsue Shimane 6908504 Japan

Simulation-based verification of hardware designs, in particular, register-transfer-level (RTL) designs, has been widely used, and has been one of the major bottlenecks in design processes. One of the approaches is coverage-driven verification, of its target is improvement of some metric called coverage. In a prior work of ours, we have proposed a coverage-driven verification using both randomly generated simulation patterns and patterns generated by a SAT (satisfiability) solver, and have shown its effectiveness. In this paper, we extend this approach with an SMT (satisfiability modulo theory) solver, which can handle arithmetic relations among integer, floating-point or bit-vector variables. Experimental results show that the more arithmetic modules are included, the more an SMT-based method gets superior to the method using only a SAT solver.

关键词： RTL verification coverage-driven verification SAT solver SMT solver automated testbench

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coverage-driven Design verification Using a Diverse SAT Solver

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2017年第7期E100A卷 1481-1487页

作者： Kakiuchi, Yosuke Hamaguchi, Kiyoharu Hiroshima Inst Technol Fac Appl Informat Sci Dept Comp Sci Hiroshima 7315193 Japan Shimane Univ Dept Math & Comp Sci Matsue Shimane 6908504 Japan

verification of logic designs has been a long-standing bottleneck in the process of hardware design, where its automation and improvement of efficiency has demanding needs. Mainly simulation-based verification has been used for this purpose, and recently, coverage-driven verification has been widely used, of which target is improvement of some metric called coverage. Our target is the metric called toggle coverage. To find input patterns which cause some toggles on each signal, a SAT solver could be used, but this is computationally costly. In this paper, we study the effect of combination of random simulation and usage of a SAT solver. In particular, we use a SAT solver which can find multiple "diverse" solutions. With this solver, we can avoid generating similar patterns, which are unlikely to improve coverage. The experimental results show that, a small number of calls of a SAT solver can improve entire toggle coverage effectively, compared with simple random simulation.

关键词： RTL verification coverage-driven verification sat solver auomated testbench

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AUTOMATED FUNCTIONAL coverage driven verification WITH UNIVERSAL verification METHODOLOGY

AUTOMATED FUNCTIONAL COVERAGE DRIVEN VERIFICATION WITH UNIVE...

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作者： Martti Tiikkainen University of Oulu

学位级别：硕士

In this Master's thesis, the validity of Universal verification Methodology in digital design verification is studied. A brief look into the methodology's history is taken, and its unique properties and object-oriented features are presented. Important coverage topics in project planning are discussed, and the two main types of coverage, code and functional coverage, are explained and the methods how they are captured are presented. The practical section of this thesis shows the implementation of a monitoring environment and an Universal verification Methodology environment. The monitoring environment includes class-based components that are used to collect functional coverage from an existing SystemVerilog test bench. The Universal verification Methodology environment uses the same monitoring system, but a different driving setup to stress the design under test. coverage and simulation performance values are extracted and from all test benches and the data is compared. The results indicate that the Universal verification Methodology environment incorporating constrained random stimulus is capable of faster simulation run times and better code coverage values. The simulation time measured was up to 26 % faster compared to a module-based environment.

关键词： Universal verification Methodology coverage coverage-driven verification methodology comparison

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Components for coverage-driven verification of Floating-Point Units 9

Components for Coverage-Driven Verification of Floating-Poin...

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9th Southern Conference on Programmable Logic (SPL)

作者： Goni, Oscar Todorovich, Elias Univ Nacl Ctr Prov Buenos Aires INTIA Inst Buenos Aires DF Argentina

ISBN: (纸本)9781479968480

This work presents the application of a mixed strategy that combines Constrained Random Tests (CRT) and coverage driven verification (CDV) as well as the development of a coverage model for Floating Point Unit (FPU) designs. The proposed strategy is materialized in two key verification components for functional verification: an input generator and a verification monitor. The generator module creates random input operands based on constraints for each operation. The monitor component not only checks the result but also indicates which cases have not been tested and estimates how much of the design functionality has been tested. Tests show that using CRT-only strategy the functional does not reach the complete coverage. However, using the proposed coverage driven verification approach not only reaches 100% coverage but also speeds up the verification up to 4.5x.

关键词： floating point arithmetic formal verification system monitoring CDV CRT FPU constrained random tests coverage driven verification coverage-driven verification floating-point units functional verification input generator random input operands verification monitor Adders Field programmable gate arrays Generators Hardware Libraries Monitoring Standards Field programmable gate arrays FLOATING POINTS floating point arithmetic verification system monitoring adders dynamos coverage Canine distemper morbillivirus Formal verification CATHODE RAY TUBE COOLANT RETURN TANK Computer hardware Libraries

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Automation of Processor verification Using Recurrent Neural Networks 18

Automation of Processor Verification Using Recurrent Neural ...

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18th International Workshop on Microprocessor and SOC Test, Security and verification (MTV)

作者： Fajcik, Martin Smrz, Pavel Zachariasova, Marcela Brno Univ Technol Dept Comp Graph & Multimedia Brno Czech Republic Brno Univ Technol Dept Comp Syst Brno Czech Republic

ISBN: (纸本)9781538633519

When considering simulation-based verification of processors, the current trend is to generate stimuli using pseudorandom generators (PRGs), apply them to the processor inputs and monitor the achieved coverage of its functionality in order to determine verification completeness. Stimuli can have different forms, for example, they can be represented by bit vectors applied to the input ports of the processor or by programs that are loaded directly into the program memory. In this paper, we propose a new technique dynamically altering constraints for PRG via recurrent neural network, which receives a coverage feedback from the simulation of design under verification. For the demonstration purposes we used processors provided by Codasip as their coverage state space is reasonably big and differs for various kinds of processors. Nevertheless, techniques presented in this paper are widely applicable. The results of experiments show that not only the coverage closure is achieved much sooner, but we are able to isolate a small set of stimuli with high coverage that can be used for running regression tests.

关键词： Functional verification Automation of verification Neural network Recurrent Neural Network Hopfield Network UVM coverage-driven verification Optimization Problem Combinatorial Optimization

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Generátor změn obrazu burzy

Generátor změn obrazu burzy

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作者： Cienciala, Ondřej Brno University of Technology

Tento dokument analyzuje zprávy zasílané burzami NYSE Arca a ISE a popisuje návrh generátoru, který generuje zprávy měnící obraz burzy. Lze ho využít pro testová... 详细信息

Tento dokument analyzuje zprávy zasílané burzami NYSE Arca a ISE a popisuje návrh generátoru, který generuje zprávy měnící obraz burzy. Lze ho využít pro testování programů, které pracují s informacemi zasílanými elektronickými burzami. Jsou popsány techniky verifikace řízené pokrytím a generování náhodných vstupních vektorů. Generování zpráv je založeno na XML šabloně, díky čemuž může být generátor použit pro různé burzy.

关键词： generátor změn obrazu burzy NYSE Arca ISE funkční verifikace náhodné vstupní vektory verifikace řízená pokrytím exchange updates generator NYSE Arca ISE functional verification constrained-random messages coverage-driven verification Text

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