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International Conference on Communication Systems and Network Technologies (CSNT)

作者： Keshav Kumar K.R. Ramkumar Amanpreet Kaur Somanshu Choudhary Chitkara University Institute of Engineering and TechnologyChitkara University Punjab India

ISBN: (数字)9781728149769

ISBN: (纸本)9781728149776

In the past recent years the idea towards secure data communication is increasing day by day. The secure communication is being achieved by applying various cryptographic algorithms on the data which is to be transferred over wireless networks. The different cryptographic algorithms that are generally practiced in the current cyber world are Advanced Encryption Standard (AES), Data Encryption Standard (DES), RSA algorithm, Message Digest 5 (MD5), Secure Hash algorithm (SHA). All these algorithms are highly secured with sound and complex mathematical computations that makes the hacker tedious to breach the data which is protected by these algorithm. The hardware implementation of algorithms enhances the speed, efficiency and reliability of security standards. In this work the Field Programmable Gate Array (FPGA) implementation of various cryptographic algorithms is discussed in details. The main motivation behind the FPGA implementations of Security algorithms is to increase the speed and decrease delays of software implementations. There are millions of logic gates that are clustered in FPGA, this brings new innovations to existing algorithms. This paper surveyss the parameters such as throughput, operating frequency, number of slice registers used and number of clock cycles of FPGA that have the major role in execution process of cryptographic algorithms. Comparative analysis on hardware implementation of security algorithms on different FPGA's is also done.

关键词： FPGA cryptographic algorithm Secure Communication Throughput Frequency Clock cycles Slice registers Field programmable gate arrays Communication system security algorithms Throughput encryption algorithm clock cycle Safety standards

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Implementation of ARIA cryptographic Modules based on ARM9 Devices

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INTERNATIONAL JOURNAL OF SECURITY AND ITS APPLICATIONS 2014年第2期8卷 243-250页

作者： Yi, Okyeon Yun, Seunghwan Park, Myungseo Song, HaengGwon Kookmin Univ Dept Math Seoul South Korea

Information over Internet needs to be communicated secure and prompt. But every cryptographic algorithm of the information requires extra time and memory space for execution in the systems such as PC or smart device. In this paper, an actual cost of speed and memory for a popular smart device environment such as ARM9 with Linux is presented so that the performance is enough to serve wired or wireless data transmission from DCU for smart grid systems or Full HD CCTV cameras.

关键词： cryptographic algorithm ARIA ARM9 cryptographic Module Validation Program

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Cooperative Model Reconstruction for cryptographic Protocols Using Visual Languages

Cooperative Model Reconstruction for Cryptographic Protocols...

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15th International Workshop on Groupware - Design, Implementation, and Use

作者： Weyers, Benjamin Luther, Wolfram Baloian, Nelson Univ Duisburg Essen INKO Lotharstr 65 Duisburg Germany Univ Chile Dept Comp Sci Santiago Chile

ISBN: (纸本)9783642042157

Cooperative work in learning environments has been shown to be a successful extension to traditional learning systems due to the great impact of cooperation on students' motivation and learning success. In this paper we describe a new approach to cooperative construction of cryptographic protocols. Using an appropriate visual language (VL), students describe a protocol step by step, modeling subsequent situations and alternating this with the creation of a concept keyboard (CK) describing the operations in the protocol. The system automatically generates a colored Petri subnet that is matched against an existing action logic specifying the protocol. Finally, the learners implement role-dependent CKs in a cooperative workflow and perform a role-play simulation.

关键词： Cooperative construction cryptographic algorithm learning environment dialog and interaction logic modeling

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A High-Efficiency Reconfigurable cryptographic Processor

A High-Efficiency Reconfigurable Cryptographic Processor

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IEEE International Conference on Integrated Circuits and Microsystems (ICICM)

作者： Wang, Shoucheng Xu, Jinhui Yan, Yingjian Li, Gongli Inst Informat Sci & Technol Dept Microelect Zhengzhou Peoples R China Henan Normal Univ Coll Comp & Informat Engn Xinxiang Peoples R China

ISBN: (纸本)9781509028146

With the significant attention to information security, mobile terminals such as smartphone always be demand for integrating cryptographic processor. In this paper, a high-efficiency reconfigurable cryptographic processor is presented. Integrating small amounts of computing units designed by reconfigurable technology and developing instruction level parallelism of different operations in a block and among multiple blocks, the proposed architecture can improve the performance of cryptographic algorithm under the condition of limited resources. The processor was simulated and synthesized in 65nm CMOS process. Experimental results show that the processor is small area and high throughput, and outperforms the state-of-the-art processors in area efficiency.

关键词： cryptographic algorithm processor reconfigure technology parallelism throughput

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Hardware-Assisted Security Mechanism: the Acceleration of cryptographic Operations with Low Hardware Cost

Hardware-Assisted Security Mechanism: the Acceleration of Cr...

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IEEE 29th International Performance Computing and Communications Conference

作者： Chang, Jed Kao-Tung Liu, Shaoshan Gaudiot, Jean-Luc Liu, Chen Univ Calif Irvine Dept Elect Engn & Comp Sci Irvine CA 92697 USA Florida Int Univ Dept Elect & Comp Engn Miami FL 33174 USA

This paper presents generic cryptographic accelerator. Certain ""hotspot function"" are found in the cryptographic algorithm which consume a substantial amount of execution time of the specific alg... 详细信息

ISBN: (纸本)9781424493289

关键词： INTEL performance analyzer Intel64-based machines VTune cryptographic algorithm cryptography generic cryptographic accelerator hardware-assisted security mechanism: hotspot function low hardware cost microprocessor chips software performance software perf

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Performance Evaluation of Firmware cryptographic Modules on Various MCU Environments 3

Performance Evaluation of Firmware Cryptographic Modules on ...

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3rd International Conference on Platform Technology and Service (PlatCon)

作者： An, Hyunjung Yun, Seunghwan Yi, Okyeon Kookmin Univ Grad Sch Dept Financial Informat Secur Seoul South Korea Korea Univ Ctr Informat Secur Technol Seoul South Korea Kookmin Univ Dept Math Seoul South Korea

ISBN: (纸本)9781467386852

With the development of IoT(Internet of Things), the combination of ICT(Information and Communications Technologies) is active in devices and systems on off-line and the Hyper Connectivity Age is becoming. This provides convenience and usefulness to users, at the same time provides threats of IT security issue to users. It is possible to utilize the cryptographic module in order to solve the security problems. However applying a cryptographic module in legacy devices gives considerably greater effect on the limited resource of devices and system itself. So it is necessary to select an appropriate level of device environment in order to solve this problem. Therefore, in this paper, after shipping the firmware cryptographic module in a similar environment to MCU chips well known relatively large, it is trying to measure the processing speed of cryptographic functions and to compare and to analyze. It is expected that there will be able to provide an indication of choice of devices for applying the cryptographic functions.

关键词： IoT Security cryptographic algorithm Micro Controller Unit Firmware

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Systematic Testing of Post-Quantum cryptographic Implementations Using Metamorphic Testing 4

Systematic Testing of Post-Quantum Cryptographic Implementat...

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IEEE/ACM 4th International Workshop on Metamorphic Testing (MET)

作者： Pugh, Sydney Raunak, M. S. Kuhn, D. Richard Kacker, Raghu Loyola Univ Maryland Dept Comp Sci Baltimore MD 21210 USA NIST Gaithersburg MD 20899 USA

ISBN: (纸本)9781728122359

cryptographic algorithms are usually complex, and their code is highly compact. Moreover, there is often no test oracle to easily test some of these algorithms. Together these attributes make it extremely challenging to run tests and to discover bugs in them. Structural coverage based approaches such as statement or branch coverage are typically not very effective in discovering bugs in these types of programs. In this paper, we investigate the effectiveness of a systematic testing approach for discovering bugs in highly complex cryptographic algorithm implementations. In this work, we identify metamorphic relations based on the specifications of the algorithms, and design test cases such that a systematic coverage of the input space is achieved. Our results show that this approach is highly effective in discovering faults in complex cryptographic implementations.

关键词： cryptographic algorithm Post-quantum Cryptography Metamorphic Testing

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T-depth reduction method for efficient SHA-256 quantum circuit construction

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IET INFORMATION SECURITY 2023年第1期17卷 46-65页

作者： Lee, Jongheon Lee, Sokjoon Lee, You-Seok Choi, Dooho Univ Sci & Technol UST Dept Informat Secur Engn Daejeon South Korea Elect & Telecommun Res Inst ETRI Cryptog Engn Res Sect Daejeon South Korea Gachon Univ Dept Comp Engn Smart Secur Seongnam South Korea Korea Univ Sejong Coll Sci & Technol Dept AI Cyber Secur Sejong 30019 South Korea

To perform a quantum brute force attack on a cryptosystem based on Grover's algorithm, it is necessary to implement a quantum circuit of the cryptographic algorithm. Therefore, an efficient quantum circuit design of a given cryptographic algorithm is essential, especially in terms of quantum security analysis, and it is well known that T-depth should be reduced for time complexity efficiency. In this paper, the authors propose a novel technique to reduce T-depth (and T-count) when some quantum circuits located in between two Toffoli-gates are interchangeable with a controlled phase gate (CP gate), and the authors apply this technique to five types of quantum adders, reducing T-depth by more than 33%. The authors also present new SHA-256 quantum circuits which have a critical path with only three quantum adders while the critical paths of quantum circuits in the previous studies consist of seven or 10 quantum adders, and the authors also apply our technique to the proposed SHA-256 quantum circuits. Four versions of SHA-256 quantum circuit are presented. Among the previous results, T-depth of the circuit with the smallest Width (the number of qubits) 801 was approximately 109,104. On the other hand, T-depth of the proposed SHA-256 quantum circuit with the Width 797 is 16,055, which is remarkably reduced by about 85%. Another proposed quantum circuit only requires 768 qubits, which is the smallest Width compared to the previous results to the best of our knowledge. Furthermore, one other version is the most time-efficient circuit with an overall Toffoli-depth (and T-depth) that is less than 5000.

关键词： time complexity efficiency quantum brute force attack Cryptography Digital circuit design, modelling and testing SHA-256 quantum circuit construction Quantum computing techniques cryptosystem Other logic elements T-depth reduction method Logic design methods quantum computing Grovers algorithm quantum security analysis Security aspects of hardware controlled phase gate adders Quantum computation quantum circuit design cryptographic algorithm Toffoli-gates Data security Logic circuits Logic and switching circuits quantum gates quantum adders logic design cryptography computational complexity

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Security-aware optimization for ubiquitous computing systems with SEAT graph approach

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JOURNAL OF COMPUTER AND SYSTEM SCIENCES 2013年第5期79卷 518-529页

作者： Qiu, Meikang Zhang, Lei Ming, Zhong Chen, Zhi Qin, Xiao Yang, Laurence T. Univ Kentucky Dept Elec & Comp Engr Lexington KY 40506 USA Univ Texas Dallas Dept Comp Sci Richardson TX 75083 USA Shenzhen Univ Coll Comp Sci & Software Engr Shenzhen 518060 GD Peoples R China Auburn Univ Dept Comp Sci & Software Engr Auburn AL 36849 USA St Francis Xavier Univ Dept Comp Sci Antigonish NS B2G 2W5 Canada

For ubiquitous computing systems, security has become a new metric that designers should consider throughout the design process, along with other metrics such as performance and energy consumption. A combination of selected cryptographic algorithms for required security services forms a security strategy for the application. In this paper, we propose methods to generate security strategies to achieve the maximal overall security strength while meeting the real-time constraint. In order to express security requirements of an application, we propose a novel graph model called Security-Aware Task (SEAT) graph model to represent real-time constraints and precedence relationships among tasks. Based on the SEAT graph approach, we propose an optimal algorithm, Integer Linear Programming Security Optimization (ILP-SOP). For the special structures such as simple path graph and tree, we, propose two dynamic programming based algorithms (DPSOP-path/tree) to generate the optimal security strategy. Experiment results demonstrate the correctness and efficiency of our proposed method. The experimental results show that, by using our proposed techniques, the security strength can be improved by 44.3% on average. (C) 2012 Elsevier Inc. All rights reserved.

关键词： Security Real-time Ubiquitous system cryptographic algorithm Schedule

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Energy efficiency of encryption schemes applied to wireless sensor networks

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SECURITY AND COMMUNICATION NETWORKS 2012年第7期5卷 789-808页

作者： Zhang, Xueying Heys, Howard M. Li, Cheng Mem Univ Newfoundland Fac Engn & Appl Sci St John NF A1B 3X5 Canada

In this paper, we focus on the energy efficiency of secure communication in wireless sensor networks (WSNs). Our research considers link layer security of WSNs, investigating both the ciphers and the cryptographic implementation schemes, including aspects such as the cipher mode of operation and the establishment of initialization vectors (IVs). We evaluate the computational energy efficiency of different symmetric key ciphers considering both the algorithm characteristics and the effect of channel quality on cipher synchronization. Results show that the computational energy cost of block ciphers is less than that of stream ciphers when data are encrypted and transmitted through a noisy channel. We further investigate different factors affecting the communication energy cost of link layer cryptographic schemes, such as the size of payload, the mode of operation applied to a cipher, the distribution of the IV, and the quality of the communication channel. A comprehensive performance comparison of different cryptographic schemes is undertaken by developing an energy analysis model of secure data transmission at the link layer. This model is constructed considering various factors affecting both the computational cost and communication cost, and its appropriateness is verified by simulation results. In conclusion, we recommend using a block cipher instead of a stream cipher to encrypt data for WSN applications and using a cipher feedback scheme for the cipher operation, thereby achieving energy efficiency without compromising the security in WSNs. Copyright (C) 2011 John Wiley & Sons, Ltd.

关键词： wireless sensor networks security encryption cryptographic algorithm stream cipher block cipher

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