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12th International Conference on Computer Supported Cooperative Work in Design

作者： Zhan, Wenfa Dept. of Educational Technology Anqing Normal College

ISBN: (纸本)9781424416509

A new test data compression scheme is introduced in this paper. The proposed scheme encodes the test data provided by the core vendor, using a new and very effective compression scheme based on OLEL coding. In this scheme, codeword is divided into two parts according to the position: odd bits and even bits. The odd bits of codeword are used to represent the length of runs. and the even bits of codeword are used to represent whether a run is finished. The length of codeword is in accordance with the distribution of the length of run in actual test data, and thus, significant compression improvements compared with the already known schemes are achieved. A simple architecture is proposed for decoding the compressed data on chip. Its hardware overhead is very low and comparable to that of the most efficient methods in the literature. Experimental results for the six largest ISCAS-89 benchmark circuits show that the proposed scheme is obviously better than the already known schemes in the aspects of compression ratio and the decompression structure, such as Golomb, FDR, and MTC coding schemes.

关键词： data compression scheme OLEL coding

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Efficient data compression methods for multidimensional sparse array operations based on the EKMR scheme

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IEEE TRANSACTIONS ON COMPUTERS 2003年第12期52卷 1640-1646页

作者： Lin, CY Chung, YC Feng Chia Univ Dept Informat Engn Taichung 407 Taiwan Natl Tsing Hua Univ Dept Comp Sci Hsinchu 300 Taiwan

In our previous work, we have proposed the extended Karnaugh map representation (EKMR) scheme for multidimensional array representation. In this paper, we propose two data compression schemes, EKMR Compressed Row/Column Storage (ECRS/ECCS), for multidimensional sparse arrays based on the EKMR scheme. To evaluate the proposed schemes, we compare them to the CRS/CCS schemes. Both theoretical analysis and experimental tests were conducted. In the theoretical analysis, we analyze the CRS/CCS and the ECRS/ECCS schemes in terms of the time complexity, the space complexity, and the range of their usability for practical applications: In experimental tests, we compare the compressing time of sparse arrays and the execution time of matrix-matrix addition and matrix-matrix multiplication based on the CRS/CCS and the ECRS/ECCS schemes. The theoretical analysis and experimental results show that the ECRS/ECCS schemes are superior to the CRS/CCS schemes for all the evaluated criteria, except the space complexity in some cases.

关键词： data compression scheme sparse array operation multidimensional sparse array Karnaugh map sparse ratio

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An efficient data compression method for the Davidson subspace diagonalization scheme

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THEORETICA CHIMICA ACTA 1995年第6期92卷 339-349页

作者： Dachsel, H Lischka, H UNIV VIENNA INST THEORET CHEM & STRAHLENCHEM A-1090 VIENNA AUSTRIA

A flexible and efficient compression scheme for the expansion and product vectors Hamiltonian matrix times expansion vectors is presented within the Davidson diagonalization method. Our approach is based on an error analysis of the energy in terms of the aforementioned vectors and on a compression scheme for representing floating point numbers with a variable length mantissa. For a selection of typical quantum chemical test cases total saving factors of up to ten are reported. The method is expected to work especially well for extended multireference CI and full CI cases. As a general outcome of our analysis we obtain limits of possible sizes of a CI expansion within the Davidson procedure in relation to the energy and the desired accuracy of the energy assuming the usual IEEE floating point standard.

关键词： Davidson procedure data compression scheme error analysis variable floating point representation

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AccEPT: An Acceleration scheme for Speeding up Edge Pipeline-Parallel Training

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IEEE TRANSACTIONS ON MOBILE COMPUTING 2024年第12期23卷 10938-10951页

作者： Chen, Yuhao Yan, Yuxuan Yang, Qianqian Shu, Yuanchao He, Shibo Shi, Zhiguo Chen, Jiming Zhejiang Univ State Key Lab Ind Control Technol Hangzhou 310027 Peoples R China Hangzhou Dianzi Univ Hangzhou 310027 Peoples R China

It is usually infeasible to fit and train an entire large deep neural network (DNN) model using a single edge device due to the limited resources. To facilitate intelligent applications across edge devices, researchers have proposed partitioning a large model into several sub-models, and deploying each of them to a different edge device to collaboratively train a DNN model. However, the communication overhead caused by the large amount of data transmitted from one device to another during training, as well as the sub-optimal partition point due to the inaccurate latency prediction of computation at each edge device can significantly slow down training. In this paper, we propose AccEPT, an acceleration scheme for accelerating the edge collaborative pipeline-parallel training. In particular, we propose a light-weight adaptive latency predictor to accurately estimate the computation latency of each layer at different devices, which also adapts to unseen devices through continuous learning. Therefore, the proposed latency predictor leads to better model partitioning which balances the computation loads across participating devices. Moreover, we propose a bit-level computation-efficient data compression scheme to compress the data to be transmitted between devices during training. Our numerical results demonstrate that our proposed acceleration approach is able to significantly speed up edge pipeline parallel training up to 3 times faster in the considered experimental settings.

关键词： Training Computational modeling data models Performance evaluation Pipelines Servers Pipeline processing Adaptive quantization bitwise compression data compression scheme distributed parallel edge training

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Memory Optimisation for Hardware Induction of Axis-parallel Decision Tree

Memory Optimisation for Hardware Induction of Axis-parallel ...

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2014 International Conference on Reconfigurable Computing and FAGAs

作者： Cheng, Chuan Bouganis, Christos-Savvas Imperial Coll London Dept Elect & Elect Engn South Kensington Campus London England

ISBN: (纸本)9781479959440

In data mining and machine learning applications, the Decision Tree classifier is widely used as a supervised learning method not only in the form of a stand alone model but also as a part of an ensemble learning technique (i.e. Random Forest). The induction of Decision Trees (i.e. training stage) involves intense memory communication and inherent parallel processing, making an FPGA device a promising platform for accelerating the training process due to high memory bandwidth enabled by the embedded memory blocks in the device. However, peak memory bandwidth is reached when all the channels of the block RAMs on the FPGA are free for concurrent communication, whereas to accommodate large data sets several block RAMs are often combined together making unavailable a number of memory channels. Therefore, efficient use of the embedded memory is critical not only for allowing larger training dataset to be processed on an FPGA but also for making available as many memory channels as possible to the rest of the system. In this work, a data compression scheme is proposed for the training data stored in the embedded memory for improving the memory utilisation of the device, targeting specifically the axis-parallel decision tree classifier. The proposed scheme takes advantage of the nature of the problem of the decision tree induction and improves the memory efficiency of the system without any compromise on the performance of the classifier. It is demonstrated that the scheme can reduce the memory usage by up to 66% for the training datasets under investigation without compromise in training accuracy, while a 28% reduction in training time is achieved due to extra processing power enabled by the additional memory bandwidth.

关键词： concurrency control data compression data mining decision trees field programmable gate arrays learning (artificial intelligence) parallel processing pattern classification FPGA device axis-parallel decision tree classifier concurrent communication data compression scheme decision tree induction embedded memory blocks ensemble learning technique hardware induction machine learning memory communication memory optimisation memory utilisation supervised learning method training process data compression Decision trees Field programmable gate arrays Hardware Random access memory Training Training data

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Light field compression based on predict ion propagating and wavelet packet

Light field compression based on predict ion propagating and...

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International Conference on Image Processing (ICIP 2004)

作者： Xu, D Dai, QH Xu, WL Tsinghua Univ Dept Automat Beijing 100084 Peoples R China

ISBN: (纸本)0780385543

A novel data compression scheme of light field is presented. Different from the prior codecs, we perform image predicting and data coding in a set of subbands not directly in original images. In our approach, firstly the original images are decomposed into subbands using wavelet packet transform, and the corresponding wavelet packet bases are divided into two parts: the predictable bases and the unpredictable bases by some criterions. In coding, a propagating algorithm and a rhombuses structure is used, and the subbands corresponding to the basis in predictable and unpredictable bases are added sequently by relative energy until the reconstructing images meet the pre-established reconstruction quality. Experiments for two standard light fields verify the efficiency of our approach.

关键词： image reconstruction image coding codecs data compression wavelet transforms light field compression data compression scheme codecs data coding wavelet packet transform predictable bases unpredictable bases propagating algorithm reconstruction quality

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