Procedural models can simulate an object's behavior as well as its appearance. When combined with dataflow methods, they provide a useful approach to image composition and animation.
Procedural models can simulate an object's behavior as well as its appearance. When combined with dataflow methods, they provide a useful approach to image composition and animation.
Programmability with increased performance? New strategies to attain this goal include two approaches to dataflow architecture: dataflow multiprocessors and the cell block architecture.
Programmability with increased performance? New strategies to attain this goal include two approaches to dataflow architecture: dataflow multiprocessors and the cell block architecture.
We present a new type of soft-core processor called the "data-flow Soft-Core" that can be implemented through FPGA technology with adequate interconnect resources. This processor provides data processing bas...
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We present a new type of soft-core processor called the "data-flow Soft-Core" that can be implemented through FPGA technology with adequate interconnect resources. This processor provides data processing based on data-flow instructions rather than control flow instructions. As a result, during an execution on the accelerator of the data-flow Soft-Core, both partial data and instructions are eliminated as traffic for load and store activities. data-flow instructions serve to describe a program and to dynamically change the context of a data-flow program graph inside the accelerator, on-the-fly. Our proposed design aims at combining the performance of a fine-grained data-flow architecture with the flexibility of reconfiguration, without requiring a partial reconfiguration or new bit-stream for reprogramming it. The potential of the data-flow implementation of a function or functional program can be exploited simply by relying on its description through the data-flow instructions that reprogram the data-flow Soft-Core. Moreover, the data streaming process will mirror those present in other FPGA applications. Finally, we show the advantages of this approach by presenting two test cases and providing the quantitative and numerical results of our evaluations.
In the companion paper [1], a programmable architecture for digital signal processing is proposed that requires the partitioning of a signal processing task into multiple programs that execute concurrently. In this pa...
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In the companion paper [1], a programmable architecture for digital signal processing is proposed that requires the partitioning of a signal processing task into multiple programs that execute concurrently. In this paper, a synchronous dataflow programming method is proposed for programming this architecture, and programming examples are given. Because of its close connection with block diagrams, dataflow programming is natural and convenient for describing digital signal processing (DSP) systems. Synchronous dataflow is a special case of dataflow (large grain or atomic) in which the number of tokens consumed or produced each time a node is invoked is specified for each input or output of each node. A node (or block) is asynchronous if these numbers cannot be specified a priori. A program described as a synchronous dataflow graph can be mapped onto parallel processors at compile time (statically), so the run time overhead usually associated With dataflow implementations evaporates. Synchronous dataflow is therefore an appropriate paradigm for programming high-performance real-time applications on a parallel processor like the processors in the companion paper. The sample rates can all be different, which is not true of most current data-driven digital signal processing programming methodologies. Synchronous dataflow is closely related to computation graphs, a special case of Petri nets. In this paper, we outline the programming methodology by illustrating how nodes are defined, how data passed between nodes are buffered, and how a compiler can map the nodes onto parallel processors. We give an example of a typically complicated unstructured application: a voiceband data modem. For this example, using a natural partition of the program into functional blocks, the scheduler is able to use up to seven parallel processors with 100 percent utilization. Beyond seven processors, the utilization drops because the scheduler is limited by a recursive computation, the eq
This paper presents a Common Format for the exchange of solved load flow cases. This format is presently being used throughout most of the eastern and north central United States and parts of Canada. By publishing thr...
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This paper presents a Common Format for the exchange of solved load flow cases. This format is presently being used throughout most of the eastern and north central United States and parts of Canada. By publishing through the national organization, it is intended that a common reference be established and maintained for those who wish to use the format. The paper presents a detailed description of the format as well as procedures for making revisions and additions.
This paper describes the implementation of a dual processor system for Positron Emission Tomography (PET). Coincidence counts are collected from 2 rings of 64 bismuth germanate (BGO) detectors. The addresses of the de...
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This paper describes the implementation of a dual processor system for Positron Emission Tomography (PET). Coincidence counts are collected from 2 rings of 64 bismuth germanate (BGO) detectors. The addresses of the detector pairs having coincident events are presented to a modified gamma camera interface that increments memory locations in the host computer. At the end of each part of the scan sequence the data are stored on disk for later reconstruction. After reconstruction the final images calibrated in Bq/cc are sent over a parallel link to the second computer where they are stored on a large disk. A master scan directory is updated each time a new scan is received, archived on tape, or deleted. Programs to display the scans and combine them with data collected from blood samples to allow computation of blood flow and regional metabolism can be run by several users on the second computer.
An experimental digital data acquisition system for computerized ultrasound imaging studies is developed. The system requirements for the digital reconstruction of tomographic images from the envelope of ultrasound si...
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An experimental digital data acquisition system for computerized ultrasound imaging studies is developed. The system requirements for the digital reconstruction of tomographic images from the envelope of ultrasound signals of several megahertz are described. To effectively digitize ultrasound signals, a new digital averager is implemented. Several consecutive ultrasound signals are averaged on a real-time base to enhance the signal-to-noise ratio, to reduce the volume of the data, and to achieve a match of dataflow rates between the ultrasound signals and the usual computer input devices. The positions of the ultrasound transducers and the target are controlled by a microprocessor controller. These positions are sensed and also digitized by the averager. The averager transfers the digitized data, both the ultrasound signals and position signals, to a general-purpose computer for further data processing. Experimental data on reconstructing the cross section of a simple target from the ultrasound signals acquired by this system will be presented as an illustration.
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