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Combining data Reuse With data-level parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2009年第3期28卷 305-315页

作者： Liu, Qiang Constantinides, George A. Masselos, Konstantinos Cheung, Peter Y. K. Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2BT England Univ Peloponnese Dept Comp Sci & Technol Tripolis 22100 Greece

A nonlinear optimization framework is proposed in this paper to automate exploration of the design space consisting of data-reuse (buffering) decisions and loop-level parallelization, in the context of field-programmable-gate-array- targeted hardware compilation. Buffering frequently accessed data in on-chip memories can reduce off-chip memory accesses and open avenues for parallelization. However, the exploitation of both data reuse and parallelization is limited by the memory resources available on-chip. As a result, considering these two problems separately, e.g., first exploring data reuse and then exploring data-level parallelization, based on the data-reuse options determined in the first step, may not yield the performance-optimal designs for limited on-chip memory resources. We consider both problems at the same time, exposing the dependence between the two. We show that this combined problem can be formulated as a nonlinear program and further show that efficient solution techniques exist for this problem, based on recent advances in optimization of so-called geometric programming problems. The results from applying this framework to several real benchmarks implemented on a Xilinx device demonstrate that given different constraints on on-chip memory utilization, the corresponding performance-optimal designs are automatically determined by the framework. We have also implemented designs determined by a two-stage optimization method that first explores data reuse and then explores parallelization on the same platform, and by comparison, the performance-optimal designs proposed by our framework are faster than the designs determined by the two-stage method by up to 5.7 times.

关键词： data-level parallelization data reuse field-programmable gate-array (FPGA) hardware compilation geometric programming optimization

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Retargeting sequential image-processing programs for data parallel execution

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IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 2005年第2期31卷 116-136页

作者： Baumstark, LB Wills, LM State Univ W Georgia Dept Comp Sci Carrollton GA 30118 USA Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

New compact, low-power implementation technologies for processors and imaging arrays can enable a new generation of portable video products. However, software compatibility with large bodies of existing applications written in C prevents more efficient, higher performance data parallel architectures from being used in these embedded products. If this software could be automatically retargeted explicitly for data parallel execution, product designers could incorporate these architectures into embedded products. The key challenge is exposing the parallelism that is inherent in these applications but that is obscured by artifacts imposed by sequential programming languages. This paper presents a recognition-based approach for automatically extracting a data parallel program model from sequential image processing code and retargeting it to data parallel execution mechanisms. The explicitly parallel model presented, called multidimensional data flow ( MDDF), captures a model of how operations on data regions ( e. g., rows, columns, and tiled blocks) are composed and interact. To extract an MDDF model, a partial recognition technique is used that focuses on identifying array access patterns in loops, transforming only those program elements that hinder parallelization, while leaving the core algorithmic computations intact. The paper presents results of retargeting a set of production programs to a representative data parallel processor array to demonstrate the capacity to extract parallelism using this technique. The retargeted applications yield a potential execution throughput limited only by the number of processing elements, exceeding thousands of instructions per cycle in massively parallel implementations.

关键词： Reengineering SIMD processors data-level parallelization explicitly parallel program representation program recognition

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