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23rd IEEE International Conference on Parallel and Distributed Systems (ICPADS)

作者： Kawano, Ryuta Yasudo, Ryota Matsutani, Hiroki Koibuchi, Michihiro Amano, Hideharu Keio Univ Kohoku Ku 3-14-1 Hiyoshi Yokohama Kanagawa Japan Natl Inst Informat Chiyoda Ku 2-1-2 Hitotsubashi Tokyo Japan

ISBN: (纸本)9781538621295

Recently proposed irregular networks can reduce the latency for both on-chip and off-chip systems with a large number of computing nodes and thus can improve the performance of parallel application. However, these networks usually suffer from deadlocks in routing packets when using a naive minimal path routing algorithm. To solve this problem, we focus attention on a lately proposed theory that generalizes the turn model to maintain the network performance with deadlock-freedom. The theorems remain a challenge of applying themselves to arbitrary topologies including fully irregular networks. In this paper, we advance the theorems to completely general ones. To apply the idea of the turn model to arbitrary topologies, we introduce a concept of regions that define continuous directions of channels on an n-dimensional space. Moreover, we provide a feasible implementation of a deadlock-free routing method based on our advanced theorem. To reduce the latency and the number of required Virtual Channels (VCs) with this method, a heuristic approach is introduced to reduce the number of prohibited turns between channels. Experimental results show that the routing method based on our proposed theorem can improve the network throughput by up to 138 % compared to a conventional deterministic minimal routing method. Moreover, it can reduce the latency by up to 2.9 % compared to another fully adaptive routing method.

关键词： Interconnection Networks deadlock-free routing algorithm High Performance Computing Irregular Networks Virtual Channels

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A Generalized Theory Based on the Turn Model for deadlock-free Irregular Networks

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2020年第1期E103D卷 101-110页

作者： Kawano, Ryuta Yasudo, Ryota Matsutani, Hiroki Koibuchi, Michihiro Amano, Hideharu Keio Univ Dept ICS Yokohama Kanagawa 2230061 Japan Natl Inst Informat Tokyo 1018430 Japan

Recently proposed irregular networks can reduce the latency for both on-chip and off-chip systems with a large number of computing nodes and thus can improve the performance of parallel applications. However, these networks usually suffer from deadlocks in routing packets when using a naive minimal path routing algorithm. To solve this problem, we focus attention on a lately proposed theory that generalizes the turn model to maintain the network performance with deadlock-freedom. The theorems remain a challenge of applying themselves to arbitrary topologies including fully irregular networks. In this paper, we advance the theorems to completely general ones. Moreover, we provide a feasible implementation of a deadlock-free routing method based on our advanced theorem. Experimental results show that the routing method based on our proposed theorem can improve the network throughput by up to 138 % compared to a conventional deterministic minimal routing method. Moreover, when utilized as the escape path in Duato's protocol, it can improve the throughput by up to 26.3 % compared with the conventional up*/down* routing.

关键词： interconnection networks deadlock-free routing algorithm high performance computing irregular networks virtual channels

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Hierarchical Tori Connected Mesh Network

Hierarchical Tori Connected Mesh Network

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13th International Conference on Computational Science and Its Applications (ICCSA)

作者： Rahman, M. M. Hafizur Shah, Asadullah Fukushi, Masaru Inoguchi, Yasushi IIUM KICT Dept Comp Sci POB 10 Kuala Lumpur 50728 Malaysia Natl Def Univ Malaysia Cyber Secur Ctr Kuala Lumpur 57000 Malaysia KUET Dept Comp Sci & Engn Khulna 9203 Bangladesh

ISBN: (纸本)9783642396403

Hierarchical interconnection networks provide high performance at low cost by exploring the locality that exists in the communication patterns of massively parallel computers. A Hierarchical Tori connected Mesh Network (HTM) is a 2D-torus network of multiple basic modules, in which the basic modules are 3D-mesh networks that are hierarchically interconnected for higher-level networks. This paper addresses the architectural details of the HTM and explores aspects such as degree, diameter, cost, average distance, arc connectivity, bisection width, and wiring complexity. We also present a deadlock-free routing algorithm for the HTM using two virtual channels and evaluate the network's dynamic communication performance using the proposed routing algorithm under uniform traffic and bit-flip traffic patterns. We evaluate the dynamic communication performance of HTM, H3DM, mesh, and torus networks by computer simulation. It is shown that the HTM possesses several attractive features, including constant node degree, small diameter, low cost, small average distance, moderate (neither too low, nor too high) bisection width, small wiring complexity, and high throughput per link and very low zero load latency, which provide better dynamic communication performance than that of H3DM, mesh, and torus networks.

关键词： Interconnection network HTM network deadlock-free routing algorithm Static network performance Uniform traffic patterns Bit-Flip traffic patterns Dynamic communication performance

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A Hardware-Oriented Fault-Tolerant routing algorithm for Irregular 2D-Mesh Network-on-Chip without Virtual Channels

A Hardware-Oriented Fault-Tolerant Routing Algorithm for Irr...

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25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT)

作者： Fukushima, Yusuke Fukushi, Masaru Yairi, Ikuko Eguchi Hattori, Takeshi Sophia Univ Fac Sci & Technol Chiyoda Ku 7-1 Kioicho Tokyo 1028554 Japan Tohoku Univ Grad Sch Informat Sendai Miyagi 9808579 Japan

ISBN: (纸本)9780769542430

Due to inevitable node and link failures, developing a fault-tolerant routing control mechanism without using virtual channels (VC) becomes very attractive approach to building large-scale network-on-chips (NoCs). Although several routing control algorithms have been proposed, their complicated routing operations consume a lot of hardware resources, thus making them impractical. In this paper, we propose a novel routing control algorithm for non-VC router of irregular 2D-mesh NoCs. The basic ideas for less implementation space and high-speed routing control are to integrate routing behaviors of the traditional message-based algorithm and to simplify the ring selection. The proposed algorithm is fully analyzed its deadlock-freeness, and is successfully implemented on an FPGA to evaluate the performance. The experimental study shows that the proposed algorithm requires quite small hardware space, while keeping the same routing performance.

关键词： irregular 2D-mesh network-on-chip fault-tolerance deadlock-free routing algorithm

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Hot-Spot Traffic Pattern on Hierarchical 3D Mesh Network 3

Hot-Spot Traffic Pattern on Hierarchical 3D Mesh Network

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3rd International Conference on Advanced Computer Science Applications and Technologies (ACSAT)

作者： Rahman, M. M. Hafizur Akhand, M. A. H. Miura, Yasuyuki Inoguchi, Yasushi IIUM KICT Dept Comp Sci Kuala Lumpur 50728 Malaysia KUET Dept Comp Sci & Engn Khulna 9203 Bangladesh Shonan Inst Technol Fujisawa Kanagawa 2518511 Japan JAIST Res Ctr Adv Comp Infrastruct Nomi Ishikawa 9231292 Japan

ISBN: (纸本)9781479918454

A Hierarchical 3D-Mesh (H3DM) Network is a 2D-mesh network of multiple basic modules (BMs), in which the basic modules are 3D-torus networks that are hierarchically interconnected for higher-level networks. In this paper, we evaluate the dynamic communication performance of a H3DM network under hot-spot traffic pattern using a deadlock-free dimension order routing algorithm with minimum number of virtual channels. We have also evaluated the dynamic communication performance of the mesh and torus networks. It is shown that under most imbalance hot-spot traffic pattern H3DM network yields high throughput and low average transfer time than that of mesh and torus networks, providing better dynamic communication performance compared to those networks.

关键词： Interconnection network H3DM network deadlock-free routing algorithm Hot-spot traffic patterns Dynamic communication performance

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HTM: A New Hierarchical Interconnection Network for Future Generation Parallel Computers

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IETE TECHNICAL REVIEW 2016年第2期33卷 93-104页

作者： Rahman, M. M. Hafizur Shah, Asadullah Fukushi, Masaru Inoguchi, Yasushi Int Islamic Univ Malaysia Dept Comp Sci Kuala Lumpur Malaysia Yamaguchi Univ Grad Sch Sci & Engn Informat Syst Engn Ube Yamaguchi 755 Japan JAIST Res Ctr Adv Comp Infrastruct Nomi Japan

In this paper, we have discussed the architectural structure, static network performance, and dynamic communication performance of a new hierarchical interconnection network called hierarchical Tori connected mesh network (HTM). For the exploration of static network performance, we have evaluated degree, diameter, cost, average distance, arc-connectivity, bisection width, and wiring complexity. We have also evaluated the dynamic communication performance of HTM, its counter rival H3DM, and conventional mesh and torus networks using a deadlock-free dimension order routing using two virtual channels under uniform and non-uniform traffic patterns. The dynamic communication performance is evaluated using computer simulation. We discovered that the HTM has a number of lucrative properties. These include constant node degree, small diameter, low cost, small average distance, moderate (neither too low, nor too high) bisection width, and less wiring complexity. HTM also yields high throughput per link and very low zero load latency, which provide better dynamic communication performance than that of H3DM, mesh, and torus networks.

关键词： deadlock-free routing algorithm dynamic communication performance HTM network interconnection network static network performance traffic patterns

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New heuristic algorithms for low-energy mapping and routing in 3D NoC

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INTERNATIONAL JOURNAL OF COMPUTER APPLICATIONS IN TECHNOLOGY 2013年第1期47卷 1-13页

作者： Liu, Yanhua Ruan, Ying Lai, Zongsheng East China Normal Univ Inst Microelect Circuit & Syst Shanghai 200062 Peoples R China Nantong Univ Jiangsu Prov Key Lab ASIC Design Nantong 226000 Peoples R China

Three Dimensional Network on Chip (3D NoC), which reduces the average number of hops traversed by a packet, can achieve better performance than the traditional 2D NoC. However, when routers deliver packets in 3D NoC, more energy consumption is needed. High-energy consumption and small packaging density will cause excessive heat, which increases vulnerability of the system in performance and reliability. In this paper, we present a low-energy consumption mapping algorithm based on the symmetry of the architecture and construct a deadlock-free routing algorithm using mapping result information. Our proposed algorithms can reduce the total energy consumption of communication and achieve a good system performance under the bandwidth constraints. To evaluate the efficacy of the algorithms, we perform experiments on several benchmarks and compare the proposed algorithms with other existing algorithms. Experimental results show that, for complex benchmarks, our proposed algorithms get better results than others.

关键词： 3D NoC three dimensional network on chip low-energy consumption mapping algorithm deadlock-free routing algorithm

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