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检索条件"主题词=debugging tools"

共 23 条记录，以下是11-20 订阅

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Instruction trace analysis and enhanced debugging in embedded systems

Instruction trace analysis and enhanced debugging in embedde...

引用

SPIE-IEEE-PSP WILGA on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments

作者： Krosman, Kazimierz Warsaw Univ Technol Inst Comp Sci Ul Nowowiejska 15-19 PL-00665 Warsaw Poland

ISBN: (数字)9781510622043

ISBN: (纸本)9781510622043

In many applications microcontrollers run preemptive real-time operating systems and have to fulfill high reliability and performance requirements. debugging and an evaluation of such systems require low-level access to the microcontroller state at every execution point. The modern MCU architectures contain special hardware modules, which generate the instruction trace and transmit it via specific physical interfaces. The execution traces provide accurate details of the program's dynamic behavior. The trace information allows recreating the software context of the each executed instruction including instruction address, type of instruction, sometimes instruction arguments or the relevant branch target address. The collected data can be used for tracing the program control flow, verification of operating system operations or reliability metrics measurement (including code coverage or availability). The paper presents the original low-cost trace analyzing system for cortex-m microcontrollers. The author proposes a new methodology for the automatic trace collection during multiple test executions. The developed system provides several types of the program trace analysis. One of them is an anomaly detection of a firmware execution. The anomaly detection is based on a commonly known clustering algorithm with the distance metric designed by the author and the trace data preparation method. The usefulness of the system has been experimentally verified while testing an original embedded system.

关键词： Instruction trace debugging tools anomaly detection embedded systems

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AN ARCHITECTURE TO ASSIST MULTIMEDIA APPLICATION AUTHORS AND PRESENTATION ENGINE DEVELOPERS

AN ARCHITECTURE TO ASSIST MULTIMEDIA APPLICATION AUTHORS AND...

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IEEE International Conference on Multimedia & Expo (ICME)

作者： Santos, Rodrigo C. M. Moreno, Marcio F. Soares, Luiz Fernando G. Pontifical Catholic Univ Rio de Janeiro PUC Rio Rua Marques Sao Vicente 225 BR-22453900 Rio De Janeiro RJ Brazil

ISBN: (纸本)9781479970827

This paper presents an architecture for monitoring the presentation of multimedia declarative applications, providing feedback about variables states, object properties, media presentation times, among others. Monitoring tools that follow the proposed architecture are able to detect if visual problems are being caused by programming errors or by player malfunctioning. The architecture presents a communication protocol designed to be independent of the declarative language used in the development of multimedia applications. The main goal is to provide an open and generic architecture that can assist multimedia application authors and presentation engine developers. As an example of the architecture use, the paper also presents a monitoring tool integrated into a graphical user interface developed for the ITU-T reference implementation of the Ginga-NCL middleware.

关键词： Multimedia authoring debugging tools declarative programming languages presentation engines Ginga-NCL

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DrAST: An Inspection Tool for Attributed Syntax Trees (Tool Demo) 9

DrAST: An Inspection Tool for Attributed Syntax Trees (Tool ...

引用

9th ACM SIGPLAN International Conference on Software Language Engineering (SLE)

作者： Lindholm, Joel Thorsberg, Johan Hedin, Gorel Lund Univ Dept Comp Sci Lund Sweden

ISBN: (纸本)9781450344470

When implementing a language by means of attribute grammars, it is often useful to study example programs and their attributed trees, to understand the compiler structure, or for debugging. DrAST is a tool that allows interactive inspection of attributed trees. It is interfaced to the JastAdd metacompiler, and supports all JastAdd attribution mechanisms, such as demand evaluation, reference attributes (graph edges), and nonterminal attributes. A challenge in visualizing attributed trees is that they are large, even for small programs. To allow the user to focus on the aspects of interest, DrAST supports the interactive definition of filtered versions of the tree through a domain-specific language which allows conditional filtering based on the attributes themselves. We have used DrAST on a variety of language implementations, from tiny compilers used in teaching to a complete Java compiler.

关键词： syntax trees attribute grammars debugging tools

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A Data Extraction and debugging Framework for Large-Scale MPSoCs

A Data Extraction and Debugging Framework for Large-Scale MP...

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23rd IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Ruaro, Marcelo Chamorra, Henrique Rubin, Felipe Amory, Alexandre Moraes, Fernando G. PUCRS Univ Dept Comp Sci Porto Alegre RS Brazil

ISBN: (纸本)9781509061136

Although it is possible to design and manufacture MPSoCs with hundreds of processors, there is still a gap in the ability to debug hardware, software, and applications for such chips. Current state-of-the-art works related to MPSoC debugging suffer from poor integration, scalability in data storage, and simple graphical data representation. This work proposes a modular debugging framework to aid the software development for large-scale MPSoCs. The framework contains two parts: back-end and front-end. The back-end contains a generic model for extraction and storage of communication and computation data. The front-end comprises a graphical debugging toolset, which provides intuitive debugging tools for the communication and computation data events. A key point of the proposal is to be generic and applicable to different MPSoC architectures due to the decoupling of the back-end and the front-end components of the framework. A data extraction layer abstracts the MPSoC architecture by defining a standard structure to database insertion. The framework is validated in an MPSoC platform described in SystemC RTL (clockcycle accurate), addressing MPSoC sizes of up to 400 processors.

关键词： MPSoC Many-Core CAD tools debugging tools Frameworks

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A 20Mevps/32Mev event-based USB framework for Neuromorphic systems debugging 2

A 20Mevps/32Mev event-based USB framework for Neuromorphic s...

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2nd International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP)

作者： Rios-Navarro, Antonio Dominguez-Morales, J. P. Tapiador-Morales, R. Gutierrez-Galan, D. Jimenez-Fernandez, A. Linares-Barranco, A. Univ Seville Robot & Technol Comp Lab Seville Spain

ISBN: (纸本)9781509041961

Neuromorphic systems are engineering solutions that take inspiration from biological neural systems. They use spike- or event-based representation and codification of the information. This codification allows performing complex computations, filters, classifications and learning in a pseudo simultaneous way. Small incremental processing is done per event, which shows useful results with very low latencies. Therefore, developing this kind of systems requires the use of specialized tools for debugging and testing those flows of events. This paper presents a set of logic implementations for FPGA that assists on the development of event-based systems and their debugging. Address-Event-Representation (AER) is a communication protocol for transferring events/spikes between bio-inspired chips/systems. Real-time monitoring and sequencing, logging and playing back long sequences of events/spikes to and from memory;and several merging and splitting ports are the main requirements when developing these systems. These functionalities and implementations are explained and tested in this work. The logic has been evaluated in an Opal-Kelly XEM6010 acting as a daughter board for the AER-Node platform. It has a peak rate of 20Mevps when logging and a total of 32Mev of logging capacity on DDR when debugging an AER system in the AER-Node or a set of them connected in daisy chain.

关键词： AER event-based systems debugging tools neuromorphic system FPGA VHDL AER-Node Opal Kelly

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Clock Delta Compression for Scalable Order-Replay of Non-Deterministic Parallel Applications 15

Clock Delta Compression for Scalable Order-Replay of Non-Det...

引用

International Conference for High Performance Computing, Networking, Storage and Analysis (SC)

作者： Sato, Kento Ahn, Dong H. Laguna, Ignacio Lee, Gregory L. Schulz, Martin Lawrence Livermore Natl Lab 7000 East Ave Livermore CA 94550 USA

ISBN: (纸本)9781450337236

The ability to record and replay program execution helps significantly in debugging non-deterministic MPI applications by reproducing message-receive orders. However, the large amount of data that traditional record-and-reply techniques record precludes its practical applicability to massively parallel applications. In this paper, we propose a new compression algorithm, Clock Delta Compression (CDC), for scalable record and replay of non-deterministic MPI applications. CDC defines a reference order of message receives based on a totally ordered relation using Lamport clocks, and only records the differences between this reference logical-clock order and an observed order. Our evaluation shows that CDC significantly reduces the record data size. For example, when we apply CDC to Monte Carlo particle transport Benchmark (MCB), which represents common non-deterministic communication patterns, CDC reduces the record size by approximately two orders of magnitude compared to traditional techniques and incurs between 13.1% and 25.5% of runtime overhead.

关键词： debugging tools Non-determinism Compression

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Dynamic heap type inference for program understanding and debugging 07

Dynamic heap type inference for program understanding and de...

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34th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages

作者： Polishchuk, Marina Liblit, Ben Schulze, Chloe W. Microsoft Corp Redmond WA 98052 USA Univ Wisconsin Madison WI 53706 USA Oracle Corp Redwood Shores CA 94065 USA

ISBN: (纸本)9781595935755

C programs can be difficult to debug due to lax type enforcement and low-level access to memory. We present a dynamic analysis for C that checks heap snapshots for consistency with program types. Our approach builds on ideas from physical subtyping and conservative garbage collection. We infer a program-defined type for each allocated storage location or identify "untypable" blocks that reveal heap corruption or type safety violations. The analysis exploits symbolic debug information if present, but requires no annotation or recompilation beyond a list of defined program types and allocated heap blocks. We have integrated our analysis into the GNU Debugger (gdb), and describe our initial experience using this tool with several small to medium-sized programs.

关键词： algorithms human factors languages reliability dynamic type inference constraints debugging tools heap visualization physical subtyping conservative garbage collection

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Efficient Fault Localization During Replay of Embedded Software 41

Efficient Fault Localization During Replay of Embedded Softw...

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41st Euromicro Conference on Software Engineering and Advanced Applications 2015

作者： Eichelberger, Hanno Kropf, Thomas Ruf, Juergen Rosenstiel, Wolfgang Greiner, Thomas Univ Tubingen Dept Comp Engn Tubingen Germany Hsch Pforzheim Univ Pforzheim Germany

ISBN: (纸本)9781467375856

When testing embedded software in real world operation, remaining failures which have not been detected during unit or system testing can often be observed. The execution of these failures is traced during operation tests of the integrated embedded system to replay it for offline debugging in the laboratory. It is time-consuming to detect the root-causes of noncrashing failures in the replay manually. Dynamic analyses during replay assist the developers in fixing these failures. The implementation of dynamic analyses using standard debugging tools improves the portability to different embedded platforms. Unfortunately, fine-grained dynamic analyses with debugger tools are often not applicable in practice because they require too much runtime effort for monitoring. Our approach accelerates the analyses by monitoring in detail only the locations which are relevant for the failure. It starts with fast monitoring of method calls to detect the approximate location of the failure in the replayed execution. Afterwards, in additional replays, it detects the root-causes by monitoring in detail only the relevant executions of methods. This paper shows how our multi-level concept makes fault localization for embedded software using debugger tools applicable in practice.

关键词： fault localization debugging tools record replay embedded software

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Hypothesizer: A Hypothesis-Based Debugger to Find and Test debugging Hypotheses 23

Hypothesizer: A Hypothesis-Based Debugger to Find and Test D...

引用

36th Annual ACM Symposium on User Interface Software and Technology (UIST)

作者： Alaboudi, Abdulaziz LaToza, Thomas D. George Mason Univ Fairfax VA 22030 USA

ISBN: (纸本)9798400701320

When software defects occur, developers begin the debugging process by formulating hypotheses to explain the cause. These hypotheses guide the investigation process, determining which evidence developers gather to accept or reject the hypothesis, such as parts of the code and program state developers examine. However, existing debugging techniques do not offer support in finding relevant hypotheses, leading to wasted time testing hypotheses and examining code that ultimately does not lead to a fix. To address this issue, we introduce a new type of debugging tool, the hypothesis-based debugger, and an implementation of this tool in Hypothesizer. Hypothesis-based debuggers support developers from the beginning of the debugging process by finding relevant hypotheses until the defect is fixed. To debug using Hypothesizer, developers first demonstrate the defect, generating a recording of the program behavior with code execution, user interface events, network communications, and user interface changes. Based on this information and the developer's descriptions of the symptoms, Hypothesizer finds relevant hypotheses, analyzes the code to identify relevant evidence to test the hypothesis, and generates an investigation plan through a timeline view. This summarizes all evidence items related to the hypothesis, indicates whether the hypothesis is likely to be true by showing which evidence items were confirmed in the recording, and enables the developer to quickly check evidence in the recording by viewing code snippets for each evidence item. A randomized controlled experiment with 16 professional developers found that, compared to traditional debugging tools and techniques such as breakpoint debuggers and Stack Overflow, Hypothesizer dramatically improved the success rate of fixing defects by a factor of five and decreased the time to debug by a factor of three.

关键词： debugging debugging hypotheses debugging tools

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SReplay: Deterministic sub-group replay for one-sided communication 16

SReplay: Deterministic sub-group replay for one-sided commun...

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30th International Conference on Supercomputing, ICS 2016

作者： Qian, Xuehai Sen, Koushik Hargrove, Paul Iancu, Costin University of Southern California United States University of California Berkeley United States Lawrence Berkeley National Laboratory United States

ISBN: (纸本)9781450343619

Replay of parallel execution is required by HPC debuggers and resilience mechanisms. Up-to-date, there is no existing deterministic replay solution for one-sided communication. The essential problem is that the readers of updated data do not have any information on which remote threads produced the updates, the conventional happens-before based ordering tracking techniques are challenging to work at scale. This paper presents SReplay, the first software tool for sub-group deterministic record and replay for one-sided communication. SReplay allows the user to specify and record the execution of a set of threads of interest (sub-group), and then deterministically replays the execution of the sub-group on a local machine without starting the remaining threads. SReplay ensures sub-group determinism using a hybrid dataand order-replay technique. SReplay maintains scalability by a combination of local logging and approximative event order tracking within sub-group. Our evaluation on deterministic and nondeterministic UPC programs shows that SReplay introduces an overhead ranging from 1:3× to 29×, when running on 1,024 cores and tracking up to 16 threads. © 2016 ACM.

关键词： One-Sided Communication PGAS debugging tools

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