检索结果-内蒙古大学图书馆

CVR: A Continuously Variable Rate LDPC decoder Using Parity Check Extension for Minimum Latency

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2021年第8期93卷 855-862页

作者： Pourjabar, Sina Choi, Gwan S. Texas A&M Univ Dept Elect & Comp Engn College Stn TX 77843 USA

This paper presents a novel IEEE 802.16e (WiMAX) based decoder that performs close to the 5G code but without the expensive hardware re-development cost. The design uses an extension of the existing WiMAX parity check code to reduce the initial decoding latency and power consumption while keeping the decoder throughput at maximum. It achieves similar Frame Error Rate (FER) compared to 5G (0.1 dB off), and most notably the error curves trend down like 5G instead flooring. At FER= 10(-3)there is 0.1 dB gain in the FER code performance compared to WiMAX. An implementation of the design is a modified version of the existing fully-parallel WiMAX decoder that supports multi-rate codeword size and reduces the initial latency by 33%. Additionally, for SNR greater than 3 dB, decoding only the shorter code reduces the power consumption by 34%.

关键词： decoder architecture Parity-check matrix (PCM) extension Low latency Low-density parity-check (LDPC) codes Very large-scale integration (VLSI)

来源：评论

学校读者我要写书评

暂无评论

A 3.0 Gb/s Throughput Hardware-Efficient decoder for Cyclically-Coupled QC-LDPC Codes

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2016年第1期63卷 134-145页

作者： Lu, Qing Fan, Jianfeng Sham, Chiu-Wing Tam, Wai M. Lau, Francis C. M. Hong Kong Polytech Univ Elect & Informat Engn Dept Hong Kong Hong Kong Peoples R China

In this paper, we propose a new class of quasi-cyclic low-density parity-check (QC-LDPC) codes, namely cyclically-coupled QC-LDPC (CC-QC-LDPC) codes, and their RAM-based decoder architecture. CC-QC-LDPC codes have a simple structure and are constructed by cyclically-coupling a number of QC-LDPC subcodes. They can achieve throughput and error performance as excellent as LDPC convolutional codes, but with much lower hardware requirements. They are therefore promising candidates for future generations of communication systems such as long-haul optical communication systems. In particular, a rate-5/6 CC-QC-LDPC decoder has been implemented onto a field-programmable gate array (FPGA) and it achieves a throughput of 3.0 Gb/s at 100 MHz clock rate with 10-iteration decoding. No error floor is observed up to an E-b/N-0 of 3.50 dB, where all 1.14 x 10(16) transmitted bits have been decoded correctly.

关键词： Cyclically-coupled QC-LDPC code decoder architecture FPGA implementation QC-LDPC code

来源：评论

学校读者我要写书评

暂无评论

Design of a High-Throughput QC-LDPC decoder With TDMP Scheduling

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2015年第1期62卷 56-60页

作者： Zhao, Ming Zhang, Xiaolin Zhao, Ling Lee, Chen Beihang Univ Sch Elect & Informat Engn Beijing 100191 Peoples R China

Low-density parity-check (LDPC) codes with turbo-decoding message-passing (TDMP) scheduling can obtain good performance and high convergence rates. In addition, the min-sum (MS) algorithm can reduce the complexity. The hybrid normalized MS algorithm with TDMP scheduling is presented to achieve good performance and to lower the complexity. For a quasi-cyclic LDPC (QC-LDPC) code with a long code length, parallel degree optimization and an offset iterative sequence rule are proposed. With the proposed techniques, the data correlation problem and memory access conflicts during TDMP scheduling can be resolved so that the iteration can smoothly proceed through the reasonable division of each block row. Fabricated in the 90-nm 1-Poly 9-Metal (1P9M) CMOS process, a multimode 96 000-bit irregular QC-LDPC decoder is implemented. It attains throughputs of 1.7-3.0 Gb/s and dissipates an average power of 502 mW at an operation frequency of 100 MHz and at 10 iterations. The decoder chip area is 13.32 mm(2), with a core area of 9.73 mm(2).

关键词： decoder architecture iterative sequence min-sum (MS) algorithm parallel degree quasi-cyclic low-density parity-check (QC-LDPC) decoder turbo-decoding message-passing (TDMP) scheduling

来源：评论

学校读者我要写书评

暂无评论

A Stage-Reduced Low-Latency Successive Cancellation decoder for Polar Codes

A Stage-Reduced Low-Latency Successive Cancellation Decoder ...

引用

IEEE International Conference on Digital Signal Processing (DSP)

作者： Liu, Xing Sha, Jin Zhang, Chuan Wang, Zhongfeng Nanjing Univ Nanjing Jiangsu Peoples R China Southeast Univ Nanjing Jiangsu Peoples R China Broadcom Corp Irvine CA USA

ISBN: (纸本)9781479980581

Polar codes, which are the first capacity achieving codes, have recently become increasingly popular because of their low encoding and decoding complexity. However, the large code length required by practical applications leads to high decoding latency because the conventional successive cancellation (SC) decoder decodes bits serially. This brief first reviews the conventional SC decoder briefly. An improved SC decoder architecture is given, which reduces the decoding latency by 25% compared to the conventional one. Then a stage-reduced SC decoding algorithm and its low-latency architecture is presented. Compared with the conventional SC decoder, the proposed stage-reduced SC decoder achieves almost 50% latency reduction with no performance degradation and acceptable hardware overhead. A kind of 2-stage-reduced SC decoding algorithm is also investigated in this brief.

关键词： polar codes successive cancellation decoding stage-reduced decoder architecture

来源：评论

学校读者我要写书评

暂无评论

The Improved Turbo-decoding Message-passing Algorithm and Corresponding decoder for LDPC Based on LTE

The Improved Turbo-decoding Message-passing Algorithm and Co...

引用

IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC)

作者： Lao, Lingling Li, Lixin Zhu, Meng Zhang, Huisheng Northwestern Polytech Univ Sch Elect & Informat Xian Peoples R China

ISBN: (纸本)9781479952748

The Turbo-decoding Message-passing (TDMP) algorithm of Low-Density Parity-Check (LDPC) codes has a faster convergence speed, lower hardware implementation complexity, and less storage units than the Belief-Passing (BP) algorithms. However, because of the integer quantization operations for initial information, restriction of storage units will cause the problem of decoding information overflowing. This paper gives the reason of overflow errors, proposes the improved decoding algorithm which can partially eliminate overflow errors, and designs the corresponding decoder which only requires some extra subtractors and shift operations. We analyze the computation complexity and compute decoder throughput. Finally, we simulate the error performances of the LDPC codes over the LTE channel, and simulation results show that the proposed algorithm effectively suppresses the overflow errors with a low decoder complexity and a high throughput.

关键词： Low-Density Parity-Check (LDPC) Turbo-decoding Message-passing (TDMP) decoder architecture

来源：评论

学校读者我要写书评

暂无评论

High Energy-Efficient LDPC decoder with AVFS System for NAND Flash Memory 53

High Energy-Efficient LDPC Decoder with AVFS System for NAND...

引用

IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Zhang, Chao Mo, Jingtong Lian, Zihan He, Weifeng Shanghai Jiao Tong Univ Sch Microelect Shanghai Peoples R China

ISBN: (纸本)9781728192017

In conventional Low-Density Parity-Check (LDPC) decoders, the real-time processing performance should meet its maximum decoding iterations for all packets and the work frequency or supply voltage is always fixed at a high level, which decreases its energy efficiency. In this paper, an energy-efficient LDPC decoding architecture with an adaptive voltage-frequency scaling (AVFS) scheme is presented. According to the usage of input packet FIFO related to variable decoding iterations, the architecture can dynamically adjust decoder's work frequency and supply voltage to reduce the processing energy while meeting its real-time processing requirement. Finally, the decoder is implemented with 28 nm CMOS process. Experimental results show that our decoder has a throughput of 1590 Mb/s when the raw bit error rate (RBER) of Flash memory is up to 10(-2). The power consumption of the decoder can be reduced by 25%-62% and energy efficiency can be increased to 1.3-2.5 times under different AWGN noise.

关键词： QC-LDPC decoder architecture AVFS energy-efficient

来源：评论

学校读者我要写书评

暂无评论

Memory Efficient Column-layered decoder Design for Non-binary LDPC Codes

Memory Efficient Column-layered Decoder Design for Non-binar...

引用

IEEE International Symposium on Circuits and Systems

作者： He, Kai Sha, Jin Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210008 Jiangsu Peoples R China

ISBN: (纸本)9781467302197

Low-density parity-check (LDPC) codes constructed over the Galois field GF(q) (q>2), which are also called non-binary LDPC codes, are an extension of binary LDPC codes with significantly better performance. In this paper, an efficient column-layered decoding algorithm, which can reduce the message memory as well as the average number of iterations dramatically, is proposed for min-max decoding. In addition, a non-uniform quantization scheme is developed for reducing the word length while achieving similar performances compared to a conventional quantization scheme. Meanwhile, the corresponding decoder architecture is also proposed.

关键词： Non-binary low-density parity-check (NB-LDPC) codes min-max column-layer non-uniform quantization decoder architecture

来源：评论

学校读者我要写书评

暂无评论

Low-Complexity LDPC decoder for 5G URLLC

Low-Complexity LDPC Decoder for 5G URLLC

引用

IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)

作者： Liu, Jian-Cheng Wang, Huan-Chun Shen, Chung-An Lee, Jih-Wei Natl Taiwan Univ Sci & Technol Dept Elect & Comp Engn Taipei 106 Taiwan

ISBN: (纸本)9781538695913

This paper proposes a low-complexity low-density parity-check (LDPC) decoder architecture for 5G ultra-reliable low latency communication (URLLC). In order to reduce the hardware utilization and the influence of data dependency problem. Proposed low-complexity decoder reduces the number of multi-size shift modules of the conventional single-layer decoder from two to one by improve the method in [15]. Due to the reduction of multi-size shift modules, we also construct new matrices that generate the shift value in proposed low-complexity decoder. Using the FPGA platform of Xilinx Virtex 7, experimental results show our proposed low-complexity decoder improves the resources utilization and throughput of conventional architectures. The improvement in percentage is about 20.1% for LUTs and 6.8% for throughput. The experimental result show that our method is more efficient than [15].

关键词： low-density parity-check (LDPC) 5G ultra-reliable low latency communication (URLLC) field-programmable gate array (FPGA) decoder architecture low-complexity shift modules

来源：评论

学校读者我要写书评

暂无评论

Designing Practical Polar Codes Using Simulation-Based Bit Selection

引用

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2017年第4期7卷 594-603页

作者： Sun, Shuanghong Zhang, Zhengya Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

The frozen set selection of polar codes, known as bit selection, determines the error-correcting performance of polar codes. The original bit selection was derived for successive cancellation decoding in a binary erasure channel. Density evolution has been used to evaluate the bit error probability in binary memoryless channel, but the computational complexity is still high and the simplified versions rely on different degrees of approximations. We propose an alternative simulation-based in-order bit selection method that evaluates the error rate of each bit using Monte Carlo decoding simulations and selects the frozen set based on the bit reliability ranking. The simulation-based method does not rely on channel models and it can be applied to any practical channels in the field. The simulation can be accelerated on an FPGA platform to significantly shorten the time required to one day for a 1024-b code design. We use three examples to demonstrate the in-order bit selection method, a (256, 128) code, a (512, 256) code, and a (1024, 512) code. Compared with the codes designed using density evolution for an AWGN channel, our (256, 128) code shows a competitive BER;our (512, 256) code outperforms at low SNR;and our (1024, 512) code outperforms across a wide range of SNR by 0.3 to 0.6 dB. The algorithm and methodology are applicable to any code rate and longer code lengths.

关键词： Polar code bit selection belief propagation decoding decoder architecture FPGA emulation

来源：评论

学校读者我要写书评

暂无评论

Construction and Hardware-Efficient Decoding of Raptor Codes

引用

IEEE TRANSACTIONS ON SIGNAL PROCESSING 2011年第6期59卷 2943-2960页

作者： Zeineddine, Hady Mansour, Mohammad M. Puri, Ranjit Amer Univ Beirut Dept Elect & Comp Engn Beirut 11072020 Lebanon Microsoft Corp Redmond WA 98052 USA

Raptor codes are a class of concatenated codes composed of a fixed-rate precode and a Luby-transform (LT) code that can be used as rateless error-correcting codes over communication channels. These codes have the atypical features of dynamic code-rate, highly irregular Tanner graph check-degree distribution, random LT-code structure, and LT-precode concatenation, which render a hardware-efficient decoder implementation achieving good error-correcting performance a challenging task. In this paper, the design of hardware-efficient Raptor decoders with good performance is addressed through joint optimizations targeting 1) the code construction, 2) decoding schedule, and 3) decoder architecture. First, random encoding is decoupled by developing a two-stage LT-code construction scheme that embeds structural features in the LT-graph that are amenable to efficient implementation while guaranteeing good performance. An LT-aware LDPC precode construction methodology that ensures architectural-compatibility with the structured LT code is also proposed. Second, a decoding schedule is optimized to reduce memory cost and account for processing workload-variability caused by the varying code rate. Third, to address the problems of check-degree irregularity and hardware underutilization, a novel reconfigurable check unit that attains a constant throughput while processing a varying number of LT and LDPC nodes is presented. These design steps collectively are employed to generate serial and partially-parallel decoder architectures. A Raptor code instance constructed using the proposed method having LT data-block length of 1210 is shown to outperform or closely match the performance of conventional LDPC codes over the code-rate range [0.4, 2/3]. The corresponding hardware serial decoder is synthesized using 65-nm CMOS technology and achieves a throughput of 22 Mb/s at rate 0.4 for a BER of 10(-6), dissipates an average power of 222 mW at 1.2 V, and occupies an area of 1.77 mm(2).

关键词： Algorithms code construction decoder architecture iterative decoding low-density parity-check codes raptor codes rate-less

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：