检索结果-内蒙古大学图书馆

The decoder design and performance comparative analysis for closed-loop brain-machine interface system

COGNITIVE NEURODYNAMICS 2024年第1期18卷 147-164页

作者： Pan, Hongguang Fu, Yunpeng Zhang, Qi Zhang, Jingyuan Qin, Xuebin Xian Univ Sci & Technol Coll Elect & Control Engn Xian 710054 Shaanxi Peoples R China Xian Key Lab Elect Equipment Condit Monit Oring & Xian 710054 Peoples R China AV Xian Aviat Brake Technol Cl Ltd Xian 710061 Shaanxi Peoples R China Minist Educ Monit Oring & Power Supply Secur Key Lab Ind Internet Things & Networked Control Chongqing 400065 Peoples R China

Brain-machine interface (BMI) can convert electroencephalography signals (EEGs) into the control instructions of external devices, and the key of control performance is the accuracy and efficiency of decoder. However, the performance of different decoders obtaining control instructions from complex and variable EEG signals is very different and irregular in the different neural information transfer model. Aiming at this problem, the off-line and on-line performance of eight decoders based on the improved single-joint information transmission (SJIT) model is compared and analyzed in this paper, which can provide a theoretical guidance for decoder design. Firstly, in order to avoid the different types of neural activities in the decoding process on the decoder performance, eight decoders based on the improved SJIT model are designed. And then the off-line decoding performance of these decoders is tested and compared. Secondly, a closed-loop BMI system which combining by the designed decoder and the random forest encoder based on the improved SJIT model is constructed. Finally, based on the constructed closed-loop BMI system, the on-line decoding performance of decoders is compared and analyzed. The results show that the LSTM-based decoder has better on-line decoding performance than others in the improved SJIT model.

关键词： Brain-machine interface decoder design Off-line/on-line performance Performance comparative analysis

来源：评论

学校读者我要写书评

暂无评论

Encoder and decoder design for fault detection over networks

Encoder and decoder design for fault detection over networks

引用

IEEE International Conference on Control Applications Part of 2010 IEEE Multi-Conference on Systems and Control

作者： Li, W. Zhu, Z. C. China Univ Min & Technol Sch Mech & Elect Engn Xuzhou 221116 Peoples R China

ISBN: (纸本)9781424453634

In this paper an encoder/decoder pair with memory is designed for fault detection (FD) over networks. The basic idea is to estimate the support of the difference between the process measurement and the estimated one. Then by applying quantization with a uniform quantizer a symbol representing the quantization cell is transmitted. Firstly the channel without packet loss and bit errors is considered. The minimum data rate for system observability is discussed and fault detection performance is also analyzed in terms of FAR and FDR. Secondly the channel with packet loss and bit errors is discussed.

关键词： bit errors codecs decoder design encoder design error statistics fault detection over networks packet loss process measurement quantization telecommunication channels

来源：评论

学校读者我要写书评

暂无评论

High Speed LDPC decoder design Based on General Overlapped Message-Passing Architecture

High Speed LDPC Decoder Design Based on General Overlapped M...

引用

6th International Conference on Ubiquitous and Future Networks (ICUFN)

作者： Lin, Baihong Li, Qi Pei, Yukui Yin, Liuguo Lu, Jianhua Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Tsinghua Univ Shenzhen Res Inst EDA Lab Shenzhen 518057 Peoples R China

ISBN: (纸本)9781479934942

The design of high speed decoders with traditional partly parallel architecture for non-quasi-cycle (NQC) LDPC codes is a challenging problem due to its high memory-block consumption and the low hardware utilization efficiency. In this paper, a general overlapped message passing (GOMP) decoding algorithm is proposed to improve the hardware utilization efficiency (HUE), which overcomes the limitation of overlapped message passing (OMP) decoders proposed before. On the basis of the given codes, this algorithm nearly doubles the throughput without sacrificing double memory or causing loss in performance compared to BP algorithm. Furthermore, we present a technique called cycle bus to reduce the number of block RAMs in the multi-core decoder. Moreover, an example of a rate-2/3, length-15360 irregular LDPC code with 8.43 dB coding gain for BPSK in AWGN channel is given, whose decoders features nearly double throughput, 22.22% increase in memory 8.35% reduction in logic registers cost and more reasonable distribution in block RAMs cost.

关键词： Non-quasi-cycle low density parity-check (NQC-LDPC) cdes general overlapped message passing (GOMP) decoding decoder design cycle bus technique high speed decoder architecture

来源：评论

学校读者我要写书评

暂无评论

AVS 3D Real-time decoder design and Implementation Based on FPGA/SoC Platform

AVS 3D Real-time Decoder Design and Implementation Based on ...

引用

International Conference on Information Sciences,Machinery,Materials and Energy（ICISMME 2015）

作者： REN Peng-fei YU Hong-yang Research Institute of Electronic Science and Technology University of Electronic Science and Technology of China

AVS(audio video coding standard)Group formulates stereo-packing scheme aimed at 3D *** this paper,based on stereo-packing algorithm,using FPGA hardware accelerate module to parse the stereo-packing ES stream syntax element and cooperating with the Xilinx ZYNQ 7020 SoC development board,we complete the AVS 3D decoder on FPGA/SoC *** HDMI port to export the decoded data to the 3D display device,we get the 3D video with depth information and verify the validity of AVS 3D real-time decoder.

关键词： 3D video stereo-packing algorithm decoder design FPGA/SoC Co-platform

来源：评论

学校读者我要写书评

暂无评论

Do-DETR: enhancing DETR training convergence with integrated denoising and RoI mechanism

引用

MULTIMEDIA SYSTEMS 2025年第2期31卷 1-14页

作者： Liang, Hong Li, Yu Zhang, Qian Shao, Mingwen China Univ Petr East China Qingdao Inst Software Coll Comp Sci & Technol 66 Changjiang West Rd Qingdao 266580 Shandong Peoples R China

As the pioneering work in Transformer-based object detection, DETR has attracted widespread attention and sparked a research trend since its inception. DETR's global attention mechanism is novel in its architecture, but it takes a very long time to optimize and reach good performance. To address this issue, we introduce DO-DETR in this paper. Specifically, except for the Hungarian loss, we build a denoising module where noisy GT bounding boxes are inputted into the decoder, which trains the model to reconstruct the original boxes. This process significantly simplifies the complexity of bipartite graph matching, resulting in accelerated convergence. In the decoder part, we designed a multi-layer recurrent processing structure based on RoI, which helps the attention of DETR gradually and more accurately focus on foreground objects. Visual features are taken as glimpse features from the larger bounding box regions of RoIs in each processing stage based on the detection outcomes of the preceding stage. These glimpse features are then modeled together with the attention outputs from the previous stage, thereby alleviating the difficulty of global attention modeling. Under the ResNet-50 backbone, DO-DETR achieved the same AP (43.6) on the MSCOCO dataset in just 16 epochs, which vanilla DETR requires 500 epochs to achieve. Meanwhile, Deformable DETR took 50 epochs to achieve a similar performance. Our DO-DETR thus improved the convergence efficiency of Deformable DETR by 68%.

关键词： Accelerated model training Training efficiency Bipartite matching decoder design Object detection

来源：评论

学校读者我要写书评

暂无评论

Algorithms for optimizing the effect of English machine translation using transformer mode

引用

JOURNAL OF COMPUTATIONAL METHODS IN SCIENCES AND ENGINEERING 2025年第1期25卷 653-668页

作者： Ma, Yan Henan Open Univ Dept Humanities & Design 124 Huanghe Rd Zhengzhou 450046 Henan Peoples R China

Despite the widespread application of the Internet and the in-depth development of globalization, English machine translation still has problems such as poor translation accuracy, long translation time, and poor ROUGE (Recall-Oriented Understudy for Gisting Evaluation) and METEOR (Metric for Evaluation of Translation with Explicit ORdering) value results. In order to better promote the improvement of English machine translation effectiveness, this article introduced the Transformer model to deeply explore the effectiveness of English machine translation. Firstly, the Transformer model structure was adjusted by integrating absolute and relative positions for position encoding. Subsequently, the encoder and decoder were designed using a multi-head attention mechanism and a feedforward neural network (FNN). The dependency weight design was achieved through the attention mechanism, and the model was pre-trained. Finally, this article also evaluated the actual performance of the adjusted Transformer model in English machine translation. The research results show that in the 5th test, the average score of the adjusted Transformer model BLEU (Bilingual Evaluation Study) reached 0.6110, the translation time was 24.90 minutes, and the average values of ROUGE and METEOR were 0.6809 and 0.6098, respectively. The research results indicate that applying the adjusted Transformer model to English machine translation is completely feasible. It can improve translation accuracy, shorten translation time, and be applied to machine translation tasks to better improve translation quality and efficiency, which is of great significance for promoting cross-cultural communication.

关键词： English machine translation transformer model attention mechanism encoder design decoder design

来源：评论

学校读者我要写书评

暂无评论

Introducing Multidimensional Parallel decoder to Reduce Cost of Implementation and Latency 37th

Introducing Multidimensional Parallel Decoder to Reduce Cost...

引用

37th International Conference on Computer Applications in Industry and Engineering

作者： Mekhiel, Nagi Toronto Metropolitan Univ Dept Elect Comp & Biomed Engn Toronto ON Canada

ISBN: (纸本)9783031762727;9783031762734

The latency and complexity of decoders are critical to performance of devices such as memory and buffers. The number of locations to be accessed in an address could be in billions. We propose a multidimensional parallel decoder that divides the address space into multiple of smaller dimensions each is decoded separately in parallel. The decoding of a much smaller address is simpler compared to the decoding of the whole address space. A combinational circuit combines the outputs of the smaller numbers of decoded outputs that correspond to the different dimensions to obtain the full decoded address space. We also purpose a time multiplexed decoder that divides the address to multiple dimensions in time and uses the multidimensional parallel decoder to obtain the decoded outputs. The results of the multidimensional parallel decoder show reduction in the cost of implementation and latency by multiple folds compared to the conventional decoder.

关键词： memory systems latency of memory access complexity of implementation performance of storage systems decoder design

来源：评论

学校读者我要写书评

暂无评论

design and Efficient Hardware Implementation Schemes for Non-Quasi-Cyclic LDPC Codes

引用

Tsinghua Science and Technology 2017年第1期22卷 92-103页

作者： Baihong Lin Yukui Pei Liuguo Yin Jianhua Lu Department of Electronic Engineering Tsinghua UniversityBeijing 100084 China School of Aerospace Tsinghua UniversityBeijing 100084

The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic（NQC） Low-Density Parity-Check（LDPC） codes is a challenging problem due to its high memory-block cost and low hardware utilization efficiency. In this paper, we present efficient hardware implementation schemes for NQCLDPC codes. First, we propose an implementation-oriented construction scheme for NQC-LDPC codes to avoid memory-access conflict in the partly parallel decoder. Then, we propose a Modified Overlapped Message-Passing（MOMP） algorithm for the hardware implementation of NQC-LDPC codes. This algorithm doubles the hardware utilization efficiency and supports a higher degree of parallelism than that used in the Overlapped Message Passing（OMP） technique proposed in previous works. We also present single-core and multi-core decoder architectures in the proposed MOMP algorithm to reduce memory cost and improve circuit efficiency. Moreover, we introduce a technique called the cycle bus to further reduce the number of block RAMs in multi-core decoders. Using numerical examples, we show that, for a rate-2/3, length-15360 NQC-LDPC code with 8.43-d B coding gain for Binary PhaseShift Keying（BPSK） in an Additive White Gaussian Noise（AWGN） channel, the decoder with the proposed scheme achieves a 23.8%–52.6% reduction in logic utilization per Mbps and a 29.0%–90.0% reduction in message-memory bits per Mbps.

关键词： Non-Quasi-Cyclic(NQC) Low-Density Parity-Check(LDPC) codes decoder design Modified Overlapped Message Passing(MOMP) algorithm hardware utilization efficiency

来源：评论

学校读者我要写书评

暂无评论

Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

引用

IEEE TRANSACTIONS ON NANOTECHNOLOGY 2011年第4期10卷 891-899页

作者： Ben Jamaa, M. Haykel Cerofolini, Gianfranco De Micheli, Giovanni Leblebici, Yusuf Commissariat Energie Atom & Energies Alternat CEA F-38054 Grenoble France Univ Milano Bicocca Dept Mat Sci I-20125 Milan Italy Ecole Polytech Fed Lausanne Microelect Syst Lab CH-1015 Lausanne Switzerland

In this paper, we demonstrate the ability of the multispacer patterning technique to yield layers of polycrystalline silicon nanowires with a sublithographic pitch, by exclusively using micrometer resolution and CMOS processing steps. We characterize single spacers operating as poly-Si nanowire field effect transistors. We demonstrate also the possibility to lay a spacer perpendicularly to a set of parallel spacers in a crossbar fashion. The extrapolated cross-point density from the small 4 x 1-array is in the range of 10(10) cm(-2). We discuss the applications of this technique to improve the density of previously reported poly-SiNW memories and as a future framework for nanowire crossbars and decoders. Then we analyze the limitations and costs of the proposed technique.

关键词： Crossbar circuits decoder design memory silicon nanowires spacer technique

来源：评论

学校读者我要写书评

暂无评论

STATE DIAGRAM CONNECTIVITY AND ITS EFFECTS ON THE DECODING OF SHIFT-REGISTER-BASED CODES

引用

IEEE TRANSACTIONS ON INFORMATION THEORY 1995年第3期41卷 756-761页

作者： COLLINS, OM Department of Electrical and Computer Engineering Johns Hopkins University Baltimore MD USA

Coding performance is limited not only by Shannon's bounds but also by the complexity of decoders. decoder complexity is in turn governed by the need for the different pieces of the machine to communicate with one another. This paper calculates lower limits on the intra-system information flow for the Viterbi decoding of shift-register-based codes, e.g., convolutional codes, These limits provide practical guidance for the construction of decoders for the current generation of convolutional and trellis codes, In particular, these bounds prove that a very specialized decoder family, called graph partition decoders, have an asymptotically optimum communications growth rate, The techniques used in this paper can, moreover, be applied to the design of new (non-shift-register-based) codes which may possibly circumvent the limits derived in the paper and to the design of parallel processors.

关键词： VITERBI DECODING DE BRUIJN GRAPHS CONVOLUTIONAL CODES GRAPH PARTITIONS decoder design GRAPH THEORY

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：