This paper presents an architectural analysis for the MAP decoder hardware implementations. The use of the graphical representation of the trellis-time graph is proposed to analytically model the scheduling between di...
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ISBN:
(纸本)0780385047
This paper presents an architectural analysis for the MAP decoder hardware implementations. The use of the graphical representation of the trellis-time graph is proposed to analytically model the scheduling between different computational operations. The ALAP schedule policy for the branch metric operations is used to minimize both the branch memory size and power consumption. In addition, key architecture metrics are derived from the analytical model. Finally, FPGA implementation of various architectures are presented.
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