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Fault Modeling and Efficient testing of Memristor-Based Memory

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2021年第11期68卷 4444-4455页

作者： Liu, Peng You, Zhiqiang Wu, Jigang Liu, Bosheng Han, Yinhe Chakrabarty, Krishnendu Guangdong Univ Technol Sch Comp Guangzhou 510006 Peoples R China Hunan Univ Coll Comp Sci & Elect Engn Key Lab Embedded & Network Comp Hunan Prov Changsha 410082 Hunan Peoples R China Chinese Acad Sci Inst Comp Technol Key Lab Comp Syst & Architecture Beijing 100190 Peoples R China Duke Univ Dept Elect & Comp Engn Durham NC 27708 USA

Memristor-based memory technology is one of the emerging memory technologies, which is a potential candidate to replace traditional memories. Efficient test solutions are required to enable the quality and reliability of such products. In previous works, fault models are caused by open, short and bridge defects and parametric variations during the fabrication. However, these fault models cannot describe the bridge defects that cause the state of the faulty cell to an undefined state. In this paper, we analyze the different effects of bridge defects and aggregate their faulty behavior into new fault models, undefined coupling fault and dynamic undefined coupling fault. In addition, an enhanced March algorithm is designed to detect all the modeled faults. In one resistor crossbar with N memristors, the enhanced March algorithm requires 8N write and 7N read operations with negligible hardware overhead. To reduce the test time, a March RC algorithm is proposed based on read operations with new reference currents, which requires 4N + 2 write and 6N read operations. Analytical results show that the proposed test algorithms can detect all the modeled faults outperforming all the previous methods. Subsequently, a Design-for-Testability scheme is proposed to implement March RC algorithm with a little area overhead.

关键词： Electrical defects fault model defect-oriented testing March algorithm non-volatile memory

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testing single via related defectsin digital VLSI designs

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MICROELECTRONICS RELIABILITY 2021年 120卷 114100-114100页

作者： Mirabella, Nunzio Ricci, Maurizio Cala, Ignazio Lanza, Roberto Grosso, Michelangelo STMicroelect Srl AMS R&D Catania Italy STMicroelect Srl AMS Data Storage & Custom PMICs Agrate Brianza MB Italy STMicroelect Srl AMS GPA & RF Catania Italy STMicroelect Srl AMS R&D Turin Italy

In integrated circuit designs, the conductive connections between different layers are known as vias or cuts. Such structures are critical for digital circuit manufacturing, as they represent a common defect location. A wellestablished DfM/DfR rule suggests replicating every via instance for increasing dependability by means of redundancy. When this is not achievable, such as when area and routing layers are limited, and when the circuit is particularly congested, a mandatory requirement is that the remaining single vias must be tested. We propose an automated method for accurately evaluating test coverage of faults related to defective vias, ready for use in any digital implementation flow and for integration within EDA tools, and also providing a useful quality metric. This article extends a previously published paper on this topic [2], with the introduction of a practical approach relying on both scan-based and functional testing to meet quality requirements in terms of single via defect coverage: functional stimuli complement the automatically-generated scan pattern set to reach the desired target at a limited cost. A prototype tool implementation for single via defect coverage computation is described, and experimental results for two industrial case studies are reported.

关键词： defect-oriented testing Single via Reliability Test Design for manufacturing Design for reliability

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testing Open defects in Memristor-Based Memories

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IEEE TRANSACTIONS ON COMPUTERS 2015年第1期64卷 247-259页

作者： Hamdioui, Said Taouil, Mottaqiallah Haron, Nor Zaidi Delft Univ Technol Dept Comp Engn NL-2628 CD Delft Netherlands Univ Tekn Malaysia Melaka 76100 Malaysia

Memristor-based memory technology, also referred to as resistive RAM(RRAM), is one of the emerging memory technologies potentially to replace conventional semiconductor memories such as SRAM, DRAM, and flash. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, fabrication techniques, and reliability improvement. However, research on (manufacturing) test for yield and quality improvement is still in its infancy stage. This paper presents fault analysis and modeling for open defects based on electrical simulation, introduces fault models, and proposes test approaches for RRAMs. The fault analysis reveals that unique faults occur in addition to some conventional memory faults, and the detection of such unique faults cannot be guaranteed with just the application of traditional march tests. The paper also presents a new Design-for-Testability (DfT) concept to facilitate the detection of the unique faults. Two DfT schemes are developed by exploiting the access time duration and supply voltage level of the RRAM cells, and their simulation results show that the fault coverage can be increased with minor circuit modification. As the fault behavior may vary due to process variations, the DfT schemes are extended to be programmable to track the changes and further improve the fault/defect coverage.

关键词： Memory defects fault models defect-oriented testing design-for-testability (DfT) memristor RRAMs

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High-Quality Statistical Test Compression With Narrow ATE Interface

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2013年第9期32卷 1369-1382页

作者： Tenentes, Vasileios Kavousianos, Xrysovalantis Univ Ioannina Ioannina 45221 Greece

In this paper, we present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques and offer a very attractive unified solution that removes the barriers of existing test data compression techniques. Besides the traditional goals of high compression and short test application time, the proposed method also offers low shift switching activity and high unmodeled defect coverage at the same time. In addition, it favors multi-site testing as requires a very low pin-count interface to the automatic test equipment. Finally, contrary to existing techniques, it provides an integrated solution for testing multi-core system on chips (SoCs) as it is suitable for cores of both known and unknown structures that usually coexist in SoCs.

关键词： defect-oriented testing design for testability dft IP cores low-power scan-based testing multi-core SoC selective Huffman test data compression unmodeled defect coverage

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defect-oriented LFSR Reseeding to Target Unmodeled defects Using Stuck-at Test Sets

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2011年第12期19卷 2330-2335页

作者： Kavousianos, Xrysovalantis Tenentes, Vasileios Chakrabarty, Krishnendu Kalligeros, Emmanouil Univ Ioannina Dept Comp Sci GR-45110 Ioannina Greece Duke Univ Dept Elect & Comp Engn Durham NC 27708 USA Univ Aegean Informat & Commun Syst Engn Dept GR-83200 Samos Greece

defect screening is a major challenge for nanoscale CMOS circuits, especially since many defects cannot be accurately modeled using known fault models. The effectiveness of test methods for such circuits can therefore be measured in terms of the coverage obtained for unmodeled faults. In this paper, we present a new defect-oriented dynamic LFSR reseeding technique for test-data compression. The proposed technique is based on a new output-deviation metric for grading stuck-at patterns derived from LFSR seeds. We show that, compared to standard compression-driven dynamic LFSR reseeding and a previously proposed deviation-based method, higher defect coverage is obtained using stuck-at test cubes without any loss of compression.

关键词： defect-oriented testing dynamic reseeding embedded testing linear decompressors static reseeding

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Generation of Compact Stuck-At Test Sets Targeting Unmodeled defects

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2011年第5期30卷 787-791页

作者： Kavousianos, Xrysovalantis Chakrabarty, Krishnendu Univ Ioannina Dept Comp Sci GR-45110 Ioannina Greece Duke Univ Dept Elect & Comp Engn Durham NC 27708 USA

This letter presents a new method to generate compact stuck-at test sets that offer high defect coverage. The proposed method first selects the most effective patterns from a large N-detect repository, by using a new output deviation-based metric. Then it embeds complete coverage of stuck-at faults within these patterns, and uses the proposed metric to further improve their defect coverage. Results show that the proposed method outperforms a recently proposed competing approach in terms of unmodeled defect coverage. In many cases, higher defect coverage is obtained even than much larger N-detect test sets for several values of N. Finally, results provide the insight that, instead of using N-detect testing with as large N as possible, it is more efficient to combine the output deviations metric with multi-detect testing to get high-quality, compact test sets.

关键词： defect-oriented testing multi-detect testing

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A Test Technique and a BIST Circuit to Detect Catastrophic Faults in RF Mixers

A Test Technique and a BIST Circuit to Detect Catastrophic F...

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International Conference on Design & Technology of Integrated Systems in Nanoscale Era

作者： I. Liaperdos L. Dermentzoglou A. Arapoyanni Y. Tsiatouhas Dept. of Information Technology and Telecommunications Technological Educational Institute of Kalamata Dept. of Informatics and Telecommunications University of Athens Dept. of Computer Science University of Ioannina

ISBN: (纸本)9781612848990

A test technique and a Built-In Self-Test (BIST) circuit to detect catastrophic faults in RF Mixers is presented in this paper. During test application the Mixer is set to operate in homodyne mode and the DC levels generated at its outputs are used as test observables. These test observables are converted to digital signatures, by a simple embedded circuit, and are used to discriminate fault free from faulty Mixers. The proposed technique has been applied to a typical differential RF Mixer designed in a 0.18μm CMOS technology. Simulation results validated its efficiency to provide a high coverage of catastrophic faults which exceeds 90%.

关键词： Design for Testability Built-in-Self Test RF Mixer defect-oriented testing

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defect Coverage-Driven Window-Based Test Compression

Defect Coverage-Driven Window-Based Test Compression

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19th IEEE Asian Test Symposium (ATS)

作者： Kavousianos, Xrysovalantis Chakrabarty, Krishnendu Kalligeros, Emmanouil Tenentes, Vasileios Univ Ioannina Dept Comp Sci Ioannina Greece Duke Univ Elect Engn Dept Durham NC 27706 USA Univ Aegean Informat & Comm Syst Engn Dept Lesbos Greece

ISBN: (纸本)9780769542485

Although LFSR reseeding based on test cubes for modeled faults is an efficient test compression approach, it suffers from the drawback of limited, and often unpredictable, coverage of unmodeled defects. We present a new defect coverage-driven window-based LFSR reseeding technique, which offers both high test quality and high compression. The efficiency of the proposed encoding technique in detecting defects is boosted by an efficient "output deviations" metric for grading the calculated LFSR seeds. We show that, compared to standard compression-driven LFSR reseeding, higher defect coverage is obtained without any loss of compression.

关键词： embedded testing linear feedback shift register defect-oriented testing

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Variation-Aware Fault Modeling

Variation-Aware Fault Modeling

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19th IEEE Asian Test Symposium (ATS)

作者： Hopsch, Fabian Becker, Bernd Hellebrand, Sybille Polian, Ilia Straube, Bernd Vermeiren, Wolfgang Wunderlich, Hans-Joachim Fraunhofer IIS EAS Dresden Germany Univ Freiburg Freiburg Germany Univ Paderborn Paderborn Germany Univ Passau Passau Germany Univ Stuttgart Stuttgart Germany

ISBN: (纸本)9780769542485

To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation- aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defect-induced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45nm technology.

关键词： defect-oriented testing parameter variations delay analogue fault simulation histograms

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defect Coverage-Driven Window-Based Test Compression

Defect Coverage-Driven Window-Based Test Compression

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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Xrysovalantis Kavousianos Vasileios Tenentes Krishnendu Chakrabarty Emmanouil Kalligeros Dept. of Computer Science University of Ioannina Greece Electrical Engineering Dept. Duke University USA Information and Comm. Systems Engineering Dept. University of the Aegean Greece

关键词： embedded testing linear feedback shift register defect-oriented testing

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