Fundamental phasor estimation is one of the most important jobs to be done by the digital protective relay (DPR). However, fault signals given to DPR consist of decaying DC (DDC) components, harmonics, and noise which...
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Fundamental phasor estimation is one of the most important jobs to be done by the digital protective relay (DPR). However, fault signals given to DPR consist of decaying DC (DDC) components, harmonics, and noise which can lead to inaccuracy in phasor estimation. Hence, for accurate results, digital filtering algorithms (DFAs) are mandatory to wipe out all these unwanted components. In modern DPR, discrete Fourier transform (DFT) is extensively used DFA for fundamental phasor estimation. However, the accuracy of DFT is affected by the presence of DDC. Hence, to tackle this problem, a new real-time fast DFA based on the mathematical morphology (MM) technique is put forward. First, the DDC components are filtered out using the morphological median filter (MMF) and are subtracted from the original fault signal. Afterwards, the fundamental phasor is extracted from the residual DDC-free signal using the DFT. Several computer-simulated, EMTP-generated, and real-field fault signals are used to examine the efficacy of the proposed DFA. In addition, the proposed DFA is compared with other existing techniques. The obtained results prove that the suggested DFA has vigorous performance in the presence of multiple DDC components, noise, and severe harmonic conditions with a low computational burden and high accuracy.
In digital Signal Processing applications, the convolution with a very long sequence is often required. In order to compute convolution of long sequence, Overlap-Add method (OLA) and Overlap-Save method (OLS) method c...
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ISBN:
(纸本)9780769530505;0769530508
In digital Signal Processing applications, the convolution with a very long sequence is often required. In order to compute convolution of long sequence, Overlap-Add method (OLA) and Overlap-Save method (OLS) method can be considered The OLA and OLS are well know efficient schemes for high-order filtering. The most commonly used implementation for digital filtering algorithms are digital Signal Processors, special purpose digitalfiltering chips and Application Specific Integrated Circuits (ASICs) for large volumes. In this paper, a high performance, high throughput and area efficient architecture for the Field Programmable Gate Array (FPGAs) implementation of block convolution process is proposed The most significant aspect of the proposed method is the development of a multiplier architecture based on vertical and crosswise structure of Ancient Indian Vedic Mathematics and embedding if in OLA and OLS methods for improved efficiency. The coding is done ill VHDL (Very High Speed Integrated Circuits Hardware Description Language) and the FPGA synthesis is done using Xilinx Spartan library. The results shows that OLA and OLS method of block convolution implemented using Vedic multiplication is efficient in terms of area/speed compared to its implementation using conventional multiplier architectures.
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