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An architecture interface and offload model for low-overhead, near-data, distributed accelerators 55

An architecture interface and offload model for low-overhead...

引用

55th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Baskaran, Saambhavi Kandemir, Mahmut Taylan Sampson, Jack Penn State Univ University Pk PA 16802 USA

ISBN: (数字)9781665462723

ISBN: (纸本)9781665462723

The performance and energy costs of coordinating and performing data movement have led to proposals adding compute units and/or specialized access units to the memory hierarchy. However, current on-chip offload models are restricted to fixed compute and access pattern types, which limits software-driven optimizations and the applicability of such an offload interface to heterogeneous accelerator resources. This paper presents a computation offload interface for multi-core systems augmented with distributed on-chip accelerators. With energy-efficiency as the primary goal, we define mechanisms to identify offload partitioning, create a low-overhead execution model to sequence these fine-grained operations, and evaluate a set of workloads to identify the complexity needed to achieve distributed near-data execution. We demonstrate that our model and interface, combining features of dataflow in parallel with near-data processing engines, can be profitably applied to memory hierarchies augmented with either specialized compute substrates or lightweight near-memory cores. We differentiate the benefits stemming from each of elevating data access semantics, near-data computation, inter-accelerator coordination, and compute/access logic specialization. Experimental results indicate a geometric mean (energy efficiency improvement;speedup;data movement reduction) of (3.3;1.59;2.4)x, (2.46;1.43;3.5)x and (1.46;1.65;1.48)x compared to an out-of-order processor, monolithic accelerator with centralized accesses and monolithic accelerator with decentralized accesses, respectively. Evaluating both lightweight core and CGRA fabric implementations highlights model flexibility and quantifies the benefits of compute specialization for energy efficiency and speedup at 1.23x and 1.43x, respectively.

关键词： distributed accelerator near-data offload energy efficiency heterogeneous architecture interface

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An Architecture Interface and Offload Model for Low-Overhead, Near-Data, distributed accelerators 22

An Architecture Interface and Offload Model for Low-Overhead...

引用

Proceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture

作者： Saambhavi Baskaran Mahmut Taylan Kandemir Jack Sampson Pennsylvania State University

ISBN: (纸本)9781665462723

The performance and energy costs of coordinating and performing data movement have led to proposals adding compute units and/or specialized access units to the memory hierarchy. However, current on-chip offload models are restricted to fixed compute and access pattern types, which limits software-driven optimizations and the applicability of such an offload interface to heterogeneous accelerator resources. This paper presents a computation offload interface for multi-core systems augmented with distributed on-chip accelerators. With energy-efficiency as the primary goal, we define mechanisms to identify offload partitioning, create a low-overhead execution model to sequence these fine-grained operations, and evaluate a set of workloads to identify the complexity needed to achieve distributed near-data *** demonstrate that our model and interface, combining features of dataflow in parallel with near-data processing engines, can be profitably applied to memory hierarchies augmented with either specialized compute substrates or lightweight near-memory cores. We differentiate the benefits stemming from each of elevating data access semantics, near-data computation, inter-accelerator coordination, and compute/access logic specialization. Experimental results indicate a geometric mean (energy efficiency improvement; speedup; data movement reduction) of (3.3; 1.59; 2.4)×, (2.46; 1.43; 3.5)× and (1.46; 1.65; 1.48)× compared to an out-of-order processor, monolithic accelerator with centralized accesses and monolithic accelerator with decentralized accesses, respectively. Evaluating both lightweight core and CGRA fabric implementations highlights model flexibility and quantifies the benefits of compute specialization for energy efficiency and speedup at 1.23× and 1.43×, respectively.

关键词： distributed accelerator near-data offload energy efficiency heterogeneous architecture interface

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