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Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using distributed arithmetic

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2016年第7期25卷 1650073-1650073页

作者： Singhal, Subodh Kumar Mohanty, Basant Kumar Jaypee Univ Engn & Technol Dept Elect & Commun Engn Guna 473226 Madhya Pradesh India

In this paper, we performed the complexity analysis of fixed-coefficient and variable-coefficient distributed arithmetic (DA)-based finite impulse response (FIR) filter structures to observe the effect of LUT decomposition on the area complexity of DA structure. The complexity analysis reveals that the area complexity of different units of DA FIR filter structure does not increase proportionately with the level of parallelism. An appropriate selection of LUT decomposition factor, and introducing higher level of parallelism in the computation could improve the area-delay efficiency of both fixed-coefficient and variable-coefficient DA-based FIR structures. Based on these findings, we have proposed bit-parallel block-based DA structures, for fixed-coefficient and variable-coefficient FIR. The proposed structures process one block of input samples and produce one block of outputs in every clock cycle. Theoretical estimate shows that the proposed fixed-coefficient structure, for block-size 8 and filter-length 32, involves eight times more ROM-LUT words, eight times more adders, two less registers, and offers eight times higher throughput-rate than the existing similar structure. For the same block-size and filter-length, the proposed variable-coefficient structure involves 7.2 times more adders, the same number of registers, eight times more MUXes, and offers eight times higher throughput than the best available similar structure. Synthesis result shows that the proposed fixed-coefficient structure for block-size 8 and filter-length 32 involve 47% less area delay product (ADP) and 42% less energy per sample (EPS) than the existing structure and offers nearly eight times higher throughput than others. For the same block-size and filter-length, the proposed structure for variable-coefficient FIR involves 71% less ADP and 65% less EPS than the similar existing structures.

关键词： Block-processing distributed arithmetic FIR filter LUT ROM

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Design and implementation of Least Mean Square adaptive FIR filter using offset binary coding based distributed arithmetic

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MICROPROCESSORS AND MICROSYSTEMS 2019年 71卷 102884-000页

作者： Kalaiyarasi, D. Reddy, T. Kalpalatha Sathyabama Inst Sci & Technol Chennai Tamil Nadu India Sri Venkateswara Coll Engn Women Tirupati Andhra Pradesh India

distributed arithmetic (DA) based architecture is an efficient technique to attain high throughput without hardware multiplier and also it is essential for bit serial operation. The DA based Finite Impulse Response (FIR) adaptive filter is well suited for hardware implementation in Field Programmable Gate Array (FPGA) device. In conventional DA the partial products of the filter coefficients have been pre-calculated and stored in Look up Table (LUT) which in turn will increase the logic elements and power. To overcome this problem DA based Least Mean Square (LMS) adaptive filter using offset binary coding (OBC) without LUT is proposed. The proposed method will reduce the logic elements by half when compared to the conventional DA based OBC filter. The Carry Save Accumulator (CSA) is used to carry out the operation of shift and accumulation. The proposed architecture is implemented in Quartus II 9.1 with the device as Stratix-EP2S15F484C3 which offers 13.72% high throughput, 56.92% reduction in logic elements, 42.84% reduction in power, 57.74% reduction in logical registers for N=16 and for N=32 the number of logical element is reduced to 80.87%, 66.66% reduction in power and 24.12% high throughput. (C) 2019 Elsevier B.V. All rights reserved.

关键词： Least Mean Square Adaptive filter distributed arithmetic Carry Save Accumulator Shift accumulator Offset binary coding

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Analysis of the convergence condition of LMS adaptive digital filter using distributed arithmetic

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2002年第6期E85A卷 1249-1256页

作者： Takahashi, K Tsunekawa, Y Tayama, N Seki, K Iwate Ind Technol Jr Coll Iwate 0283615 Japan Iwate Univ Fac Engn Morioka Iwate 0208551 Japan

An LMS adaptive digital filter using distributed arithmetic (DA-ADF) has been proposed. Cowan and others proposed the DA adaptive algorithm with offset binary coding for the simple derivation of an algorithm and the use of an odd-symmetry property of adaptive function space (AFS) [3], [5], [10]. However, we indicated that a convergence speed of this DA adaptive algorithm degraded extremely by our computer simulations [6]. To overcome these problems, we have proposed the DA adaptive algorithm generalized with two's complement representation and effective architectures. Our DA-ADF has performances of a high speed, small output latency, a good convergence speed, small-scale hardware and lower power dissipation for higher order, simultaneously. In this paper, we analyze a convergence condition of DA adaptive algorithm that has never been considered theoretically [8], [9]. From this analysis, we indicate that the convergence speed is depended on a distribution of eigenvalues of an auto-correlation matrix of an extended input signal vector [8], [9]. Furthermore, we obtain the eigenvalues theoretically. As a result, we clearly show that our DA-ADF has an advantage of the conventional DA-ADF in the convergence speed.

关键词： distributed arithmetic LMS algorithm adaptive function space convergence condition offset bias

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High Performance DIF-FFT Using Dissimilar Partitioned LUT Based distributed arithmetic

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INTERNATIONAL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS 2021年第4期67卷 631-637页

作者： Cheepurupalli, Kusma Kumari Charan, Muntha Rao, Jammu Bhaskara Noor, Mahammad S. Gayatri Vidya Parishad Coll Engn Dept ECE Visakhapatnam Andhra Pradesh India

Real-time data processing systems utilize Digital Signal Processing (DSP) functions as the base modules. Most of the DSP functions involve the implementation of Fast Fourier Transform (FFT) to convert the signals from one domain to another domain. The major bottleneck of Decimation in frequency-Fast Fourier Transform (DIF-FFT) implementation lies in using a number of Multipliers. distributed arithmetic (DA) is considered as one of the efficient techniques to implement DIF-FFT. In this approach, the multipliers are not used. The proposed technique exploits the very advantage of the look-up table by storing the Twiddle factors, thereby avoiding the multipliers required in the butterfly structure. DIF-FFT using distributed arithmetic (DIF-FFT DA) models, with different adders such as Ripple carry adder (RCA), Carry-lookahead adder (CLA), and Sklansky prefix graph adder, are proposed in this paper. The three proposed models are synthesized using Cadence 6.1 EDA tools with a 45nm CMOS technology. Compared to the traditional method, it is observed that the area is improved by 53.11%, 53.35%, and 50.15%, power is improved by 42.31%, 42.52%, and 40.39%, and delay is improved by 45.26%, 45.42%, 41.80%, respectively.

关键词： Fast Fourier Transform Adders distributed arithmetic DSP

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A Memory Efficient, Multiplierless & Modular VLSI Architecture of 1D/2D Re-Configurable 9/7 & 5/3 DWT Filters Using distributed arithmetic

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2020年第9期29卷

作者： Chakraborty, Anirban Banerjee, Ayan Indian Inst Engn Sci & Technol Elect & Telecommun Engn Dept Sibpur Howrah India

Dedicated hardware for "Discrete Wavelet Transform" (DWT) is at high demand for real-time imaging operations in any standalone electronic devices, as DWT is being extensively utilized for most of the transform-domain imagery applications. Various DWT algorithms exist in the literature facilitating its software implementations which are generally unsuitable for real-time imaging in any stand-alone devices due to their power intensiveness and huge computation time. In this paper, a convolutional DWT-based pipelined and tunable VLSI architecture of Daubechies 9/7 and 5/3 DWT filter is presented. Our proposed architecture, which mingles the advantages of convolutional and lifting DWT while discarding their notable disadvantages, is made area and memory efficient by exploiting "distributed arithmetic' (DA) in our own ingenious way. Almost 90% reduction in the memory size than other notable architectures is reported. In our proposed architecture, both the 9/7 and 5/3 DWT filters can be realized with a selection input, "mode". With the introduction of DA, pipelining and parallelism are easily incorporated into our proposed 1D/2D DWT architectures. The area requirement and critical path delay are reduced to almost 38.3% and 50% than that of the latest remarkable designs. The performance of the proposed VLSI architecture also excels in real-time applications.

关键词： DWT distributed arithmetic memory efficient digital VLSI design parallelism image decomposition PSNR

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Fast Discrete Wavelet Transformation Using FPGAs and distributed arithmetic

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International Journal of Applied Science and Engineering 2003年第2期1卷 160-171页

作者： Ali M. Al-Haj Department of Electronics Engineering Princess Sumaya University for Technology

The discrete wavelet transform has gained the reputation of being a very effective sig- nal analysis tool for many practical applications. However, due to its computation-intensive na- ture, current implementations of the transform fall short of meeting real-time processing re- quirements of most applications. This paper describes a parallel implementation of the discrete wavelet transform and its inverse using high-density field programmable logic devices (FPGAs). The implementation exploits the lookup table-based architecture of Virtex FPGAs, by reformu- lating the wavelet computation in accordance with the distributed arithmetic algorithm. Perform- ance results show that the distributed arithmetic formulation results in a considerable perform- ance gain compared with the conventional arithmetic formulation of the wavelet computation. Finally, we show that the FPGA implementation outperforms alternative software implementa- tions of the discrete wavelet transform.

关键词： Discrete wavelet transform distributed arithmetic FPGA implementation.

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An Efficient 256-Tap Parallel FIR Digital Filter Implementation Using distributed arithmetic Architecture

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Procedia Computer Science 2015年 54卷 605-611页

作者： Amita Nandal T. Vigneswarn Ashwani K. Rana Arvind Dhaka Department of ECE NIT Hamirpur Department of ECE VIT University Chennai Deparment of CSE NIT Hamripur

This paper discusses FPGA implementation of Finite Impulse Response (FIR) filters using distributed arithmetic (DA) which substitute multiply and accumulate operations with a series of Look-Up-Table (LUT) accesses. Parallel FIR digital filter can be used either for high speed or low-power applications. The distributed arithmetic provides a multiplication-free method for calculating inner products of fixed-point data, based on table lookups of pre calculated partial products. The implementation results are provided to demonstrate a high-speed and low power proposed architecture. The proposed filter is implemented in very high speed integrated circuit hardware description language (VHDL) and verified via simulation. The proposed method offers average reductions of 60% in the number of LUT, 40% reduction in occupied slices and 50% reduction in the number gates for parallel FIR filter implementation.

关键词： distributed arithmetic DSP Finite impulse response LUT MAC and parallel filters.

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Modified distributed arithmetic Concept for Implementations Targeted at Heterogeneous FPGAs

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INTERNATIONAL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS 2010年第4期56卷 345-350页

作者： Rawski, Mariusz Warsaw Univ Technol Inst Telecommun Nowowiejska 15-19 PL-00665 Warsaw Poland

distributed arithmetic (DA) plays an important role in designing digital signal processing modules for FPGA architectures. It allows replacing multiply-and-accumulate (MAC) operations with combinational blocks. The quality of implementations based on DA strongly depends on efficiency of methods that map combinational DA block into FPGA resources. Since modern FPGAs have heterogeneous structure, there is a need for quality algorithms to target these structures and the need for flexible architecture exploration aiding in appropriate mapping. The paper presents a modification of DA concept that allows for very efficient implementation in heterogeneous FPGA architectures.

关键词： distributed arithmetic FPGA heterogeneous programmable structures

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HIGH-PERFORMANCE VLSI ARCHITECTURE SUITABLE FOR CONTROL-SYSTEMS FOR STATE-SPACE DIGITAL-FILTERS USING distributed arithmetic

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ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE 1995年第5期78卷 12-21页

作者： TSUNEKAWA, Y MIURA, M Faculty of Engineering Iwate University Morioka Japan 020 Members

This paper proposes and evaluates high-performance VLSI architecture for real-time state-space digital filters used in digital signal processing and digital control. A VLSI-oriented highly parallel architecture for state-space digital filters with high sampling rate and small latency has already been proposed by the authors. To speed up and reduce hardware complexity, the distributed arithmetic (of which processing time depends on only word length) is applied to this architecture, making good use of highly accurate state-space digital filters. The very high sampling rate can be implemented independently of filter order and the number of the input and output.

关键词： STATE-SPACE DIGITAL FILTER HIGH ACCURACY distributed arithmetic HIGH-PERFORMANCE VLSI ARCHITECTURE

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B06: Advanced synthesis of digital filters based on distributed arithmetic concept for FPGAs

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IFAC Proceedings Volumes 2004年第20期37卷 198-202页

作者： Paweł Tomaszewicz Mariusz Rawski Piotr Zbysiński Warsaw University of Technology Institute of Telecommunications

This paper presents the application of distributed arithmetic in implementation of digital filter in FPGA structures. Since in this approach general purpose multipliers are replaced by combinational LUT blocks, it is possible to construct digital filters of very high performance. In this paper an application of the functional decomposition based method to LUT blocks optimisation and mapping has been investigated. This method is recognised as the best synthesis method targeted FPGA architectures, thus it allows significant improvements in digital filters implementation. The paper presents many examples confirming that decomposition allows reduction of logic cell utilisation of filter implementation based on distributed arithmetic concept with no performance degradation and even increasing it.

关键词： digital filters distributed arithmetic logic synthesis functional decomposition

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