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Multiplierless fast Fourier transform architecture

ELECTRONICS LETTERS 2007年第3期43卷 191-192页

作者： Jiang, M. Yang, B. Huang, R. Zhang, T. Y. Wang, Y. Y. Peking Univ Inst Microelect Beijing 100871 Peoples R China

A multiplierless processor architecture is proposed for hardware implementation of fast Fourier transform. distributed arithmetic is applied to simplify expensive butterfly operations and twiddle multiplications. The novel architecture can largely reduce area cost by replacing complex multipliers and adders with DA lookup tables. Both 8-bit and 16-bit 64-point FFT processors were designed, and the synthesis result shows the designs can attain much lower area cost while keeping real-time processing speed.

关键词： coprocessors Microprocessor chips Integral transforms fast Fourier transforms distributed arithmetic 8 bit Digital arithmetic methods Microprocessors and microcomputers table lookup lookup tables fast Fourier transform multiplier-less processor architecture 16 bit

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DA-Based Efficient Testable FIR Filter Implementation on FPGA Using Reversible Logic

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CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2014年第3期33卷 863-884页

作者： Nandal, Amita Vigneswaran, T. Rana, Ashwani K. Natl Inst Technol Dept Elect & Commun Engn Hamirpur 177005 Himachal Prades India VIT Univ Dept Elect & Commun Engn Madras 600127 Tamil Nadu India

This paper discusses the FPGA implementation of finite impulse response (FIR) filters using a testable reversible logic-based design. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up table (LUT) accesses. The canonical signed digit (CSD) representation is used to represent the coefficients which are compared with sum-of-powers-of-two (SOPOT) technique of coefficients representation. distributed arithmetic provides a multiplication-free method for calculating inner products of fixed-point data, based on table look-ups of pre-calculated partial products. The implementation results are provided to demonstrate a high-speed and low power proposed architecture. The proposed filter is implemented in very high speed integrated circuit hardware description language (VHDL) and verified via simulation. The reversible architecture scheme yields significantly reduced complexity, low power, and high speed features. The major concern with reversible gates is the reduction of garbage outputs and constant inputs. The proposed gate has less garbage outputs and constant inputs, which are important parameters for reversible designs. The proposed method offers average reductions of 30 % in the number of LUT, 42 % reduction in occupied slices and 38 % reduction in the number gates for low pass FIR filter implementation method. The proposed design shows 45 % improvement in performance as compared to existing one.

关键词： CSD arithmetic distributed arithmetic LUT SOPOT arithmetic Finite impulse response Garbage output Reversible logic Testability Constant input and fault detection

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A new k-winners-take-all neural network and its array architecture

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IEEE TRANSACTIONS ON NEURAL NETWORKS 1998年第5期9卷 901-912页

作者： Yen, JC Guo, JI Chen, HC Natl Lien Ho Coll Technol & Commerce Dept Elect Engn Miaoli Taiwan

In this paper, a new neural-network model called WINSTRON and its novel array architecture are proposed. Based on a competitive learning algorithm that is originated from the coarse-fine competition, WINSTRON can identify the fi larger elements or the k smaller ones in a data set. We will then prove that WINSTRON converges to the correct state in any situation, In addition, the convergence rates of WINSTRON for three special data distributions will be derived. In order to realize WINSTRON, its array architecture with low hardware complexity and high computing speed is also detailed. Finally, simulation results are included to demonstrate its effectiveness and its advantages over three existing networks.

关键词： artificial neural network k-winners-take-all competitive learning distributed arithmetic memory-based architecture systolic array

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An energy-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2005年第5期15卷 704-715页

作者： Chen, KH Guo, JI Wang, JS Yeh, CW Chen, JW Natl Chung Cheng Univ Dept Elect Engn Chiayi 621 Taiwan Natl Chung Cheng Univ Dept Comp Sci & Informat Engn Chiayi 621 Taiwan

This paper proposes a flexible hardware solution and the associated energy-aware IP core design for computing the variable-length discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) required in the MPEG4 shape-adaptive DCT/IDCT (SA-DCT/IDCT). The proposed IP core has been developed based on the design concept of programmable processors to provide the flexibility in dynamically configuring the hardware. To achieve good performance both in area and speed, we optimize the proposed IP core both in the algorithmic computational complexity and hardware complexity. Furthermore, the proposed IP core possesses the feature of energy-aware design flexibility. The simulation shows that the proposed design has 44% energy reduction at the price of 0.3-dB signal quality degradation for the image compression applications. The implementation results show that the proposed IP core costs about 3100 gates along with 16 words (1 word = 16 bits) of memory, which can achieve the real-time processing of the texture coding in MPEG4 SP@L3 and ACE@L2 CODEC system for the CIF format video at 30 frames/s with 4:2:0 color format.

关键词： common subexpression sharing distributed arithmetic MPEG4 object-based video coding shape-adaptive discrete cosine transform SIP design system-on-a-chip (SoC) design

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Delineation of Optimized Single and Multichannel Approximate DA-Based Filter Design Using Influential Single MAC Strategy for Trans-Multiplexer

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SENSORS 2024年第22期24卷 7149页

作者： James, Britto Pari Man-Fai, Leung Karuthapandian, Mariammal Dhandapani, Vaithiyanathan Vel Tech Rangarajan Dr Sagunthala R&D Inst Sci & T Chennai 600062 India Anglia Ruskin Univ Fac Sci & Engn Sch Comp & Informat Sci Cambridge CB1 1PT England Anna Univ Madras Inst Technol Chennai 600044 India Natl Inst Technol Delhi Delhi 110036 India

In this paper, a multichannel FIR filter design based on the Time Division Multiplex (TDM) approach that incorporates one multiply and add unit, regardless of the variable coefficient length and varying channels, by associating the resource sharing doctrine is suggested. A multiplier based on approximate distributed arithmetic (DA) circuits is employed for effective resource optimization. Although no explicit multiplication was conducted in this realization, the radix-8 and radix-4 Booth algorithms are utilized in the DA framework to curtail and optimize the partial products (PPs). Furthermore, the input stream is truncated with an erratum mending unit to roughly construct the partial products. For an aggregation of PPs, an approximate Wallace tree is taken into consideration to further minimize hardware expenses. Consequently, the suggested design's latency, utilized area, and power usage are largely reduced. The Xilinx Vertex device is expedited, given the synthesis of the suggested multichannel realization with 16 taps, which is simulated using the Verilog formulary. It is observed that the filter structure with one channel produced the desired results, and the system's frequency can support up to 429 MHz with a reduced area. Utilizing TSMC 180 nm CMOS technology and the Cadence RC compiler, cell-level performance is also achieved.

关键词： distributed arithmetic finite impulse response filter approximate computing FPGA multiply-accumulate unit hardware optimization

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Fixed-point error analysis and word length optimization of 8x8 IDCT architectures

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 1998年第8期8卷 935-940页

作者： Kim, S Sung, W LG Corp Inst Technol Informat Technol Lab Seoul South Korea Seoul Natl Univ Sch Elect Engn Seoul 151742 South Korea

Complete fixed-point error models that include the coefficient quantization are derived for two popular 8 x 8 two-dimensional (2-D) IDCT architectures;one is based on distributed arithmetic. and the other is the multiplier-adder chain. The error models are evaluated in the integer domain to accurately measure the effects of rounding. The analysis results show that the overall mean-square error performance (OMSE) is the most critical condition for meeting the IEEE specification (IEEE Std. 1180-1990) when the rounding scheme is employed, On the other hand, the mean error effects (OME and PME) are dominant for truncation. Finally, the analysis results are compared with those of bit-accurate simulation.

关键词： distributed arithmetic fixed-point error analysis IDCT IEEE Standard 1180-1990 word length optimization

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DA based approach for the implementation of block adaptive decision feedback equaliser

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IET SIGNAL PROCESSING 2016年第6期10卷 676-684页

作者： Prakash, Matcha Surya Shaik, Rafi Ahamed Indian Inst Technol Guwahati Elect & Elect Engn Gauhati 781039 Assam India

Adaptive decision feedback equalisers (ADFEs) are used in wireless transmission systems for mitigating the InterSymbol Interference (ISI) that occurs due to multipath propagation of the transmitted signal. In case of high speed communications which involve rapid-varying channels, fast convergent and low complexity ADFEs are required. Frequency domain block processing of signals is an effective means of handling the increased complexities in such high speed systems. However, block ADFEs being inherently non-causal, the feedback filter (FBF) suffers from the lack of unknown decisions in every block computation. In this study, the authors propose an efficient approach for the computation of these unknown decisions. For this, the authors tried to minimise a cost function based on two criteria mean-absolute difference (MAD) and mean-square difference between the ADFE output and the adder that sums up the feedforward filter (FFF) and FBF. A bank of registers which store all the symbols used in the modulation scheme is also utilised for this purpose. Using the proposed solution, the authors recast block ADFE equations in the frequency domain using distributed arithmetic (DA). The algorithm has a good convergence performance and utilises only few computations compared with the existing schemes.

关键词： equalisers feedback intersymbol interference feedforward filtering theory modulation distributed arithmetic DA based approach block adaptive decision feedback equaliser wireless transmission systems intersymbol interference ISI multipath propagation transmitted signal convergence performance distributed arithmetic modulation scheme feedforward filter mean-square difference mean-absolute difference feedback filter frequency domain block processing rapid-varying channels

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NEDA: A low-power high-performance DCT architecture

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2006年第3期54卷 955-964页

作者： Shams, AM Chidanandan, A Pan, W Bayoumi, MA Univ Louisiana Ctr Adv Comp Studies Lafayette LA 70504 USA

Conventional distributed arithmetic (DA) is popular in application-specific integrated circuit (ASIC) design, and it features on-chip ROM to achieve high speed and regularity. In this paper, a new DA architecture called NEDA is proposed, aimed at reducing the cost metrics of power and area while maintaining high speed and accuracy in digital signal processing (DSP) applications. Mathematical analysis proves that DA can implement inner product of vectors in the form of two's complement numbers using only additions, followed by a small number of shifts at the final stage. Comparative studies show that NEDA outperforms widely used approaches such as multiply/accumulate (MAC) and DA in many aspects. Being a high-speed architecture free of ROM, multiplication, and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. A hardware compression scheme is introduced to generate a butterfly structure with minimum number of additions. NEDA-based architectures for 8 x 8 discrete cosine transform (DCT) core are presented as an example. Savings exceeding 88% are achieved, when the compression scheme is applied along with NEDA. Finite word-length simulations demonstrate the viability and excellent performance of NEDA.

关键词： discrete cosine transform (DCT) distributed arithmetic inner product ROM-free multiplication

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Novel design and FPGA implementation of DA-RNS FIR filters

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JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2004年第6期13卷 1233-1249页

作者： Wang, W Swamy, MNS Ahmad, MO Indiana Univ Purdue Univ Dept Elect & Comp Engn Indianapolis IN 46202 USA Concordia Univ Dept Elect & Comp Engn Ctr Signal Proc & Commun Montreal PQ H3G 1M8 Canada

Field programmable gate array (FPGA)-based digital signal processing has been widely used in multimedia applications. By combining distributed arithmetic (DA) and residue number system (RNS) in such designs, efficient area, speed and power efficiency can be achieved. In this paper, we propose novel techniques for the design and FPGA implementation of DA-RNS finite impulse response (FIR) filters. By introducing a novel low-cost moduli set and its selection method, efficient modulo arithmetic units inside the subfilters are designed. Then, a new residue-to-binary conversion algorithm, a so-called modified DA Chinese remainder theorem, is derived to reduce the modulo operations and provide an efficient residue-to-binary converter suitable to FPGA implementation. Based on these proposed techniques, a seventh-order DA-RNS FIR filter is designed, implemented and tested by using Xilinx FPGA tools. The implementation results show that the proposed filter design consumes only 77% of the power that the existing filter(12,13) requires, while maintaining the same speed (throughput).

关键词： multimedia FIR filter distributed arithmetic residue number system Chinese remainder theorem residue-to-binary converter FPGA implementation

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Applying an XC6200 to real-time image processing

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IEEE DESIGN & TEST OF COMPUTERS 1998年第1期15卷 30-38页

作者： Woods, R Trainor, D Heron, JP Queens Univ Belfast Dept Elect & Elect Engn Belfast BT9 5AH Antrim North Ireland

This implementation of a two-dimensional discrete cosine transform demonstrates the development of a suitable architectural style for a specific technology-in this case, the Xilinx XC6200 FPGA series. The design exploits distributed arithmetic, parallelism, and pipelining to achieve a high-performance custom-computing implementation.

关键词： FPG As Image Compression Custom Computing distributed arithmetic

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