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IEEE Workshop on Signal Processing Systems

作者： Darwish, T Bayoumi, M Intel Corp Lafayette LA 70504 USA Univ Louisana Ctr Adv Comp Studies Lafayette LA USA

An energy aware DCT (Discrete Cosine Transform) architecture based on the distributed arithmetic concept is proposed. Architectures based on the distributed arithmetic concept are inherently low power as they are multiplication free algorithms. One characteristic of the DCT is that upon transformation signal energies are concentrated in only a few coefficients (less than 25%) with the rest (75%) of the coefficients being insignificant and negligible. One can skip the computation of these terms without seriously affecting the output signal quality. Exploiting this idea, we propose a low energy DCT architecture that can achieve 55% savings in the energy dissipation and 28 db in signal quality. In addition, we propose an adaptive energy aware DCT architecture that trades off energy consumption for signal quality. Using this adaptive architecture, we present a study of the effect of coefficient elimination on energy consumption and signal quality.

关键词： DCT distributed arithmetic low energy VLSI video compression

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A distributed arithmetic architecture for fast implementation of vector or matrix products

A distributed arithmetic architecture for fast implementatio...

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12th International Workshop on Systems, Signals and Image Processing

作者： Grigoriadis, G Boutalis, Y Mertzios, B Democritus Univ Thrace Dept Elect & Comp Engn GR-67100 Xanthi Greece

ISBN: (纸本)0907776205

Fast implementations of the inner product of two (nxl) vectors, of the (nxn) MVM (matrix vector multiplication) operation and (nxn) MMM (matrix matrix multiplication) operation are of paramount importance in many research fields such as signal processing, control systems and robotics. So far, the proposed distributed arithmetic (DA) architectures provide fast implementation of such products, but they require that the elements of one of the vectors contain constant a-priori known values. In this paper we propose a new general purpose DA architecture which considers that both vector or matrix elements are variable. The block diagram of the proposed hardware design is given and its performance is theoretically estimated.

关键词： distributed arithmetic vector operations

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A distributed arithmetic hardware architecture for real-time Hough-transform-based segmentation

A distributed arithmetic hardware architecture for real-time...

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18th IEEE Canadian Conference on Electrical and Computer Engineering

作者： Mayasandra, K Salehi, S Wang, W Ladak, HM Univ Western Ontario Dept Elect & Comp Engn London ON N6A 5B9 Canada Univ Western Ontario Dept Med Biophys London ON N6A 3K7 Canada Indiana Univ Purdue Univ Dept Elect & Comp Engn Indianapolis IN USA

Real-time segmentation and tracking of biopsy needles is a very important part of image-guided surgery. Since the needle appears as a straight line in medical images, the Hough transform for straight-line detection is a natural and powerful choice for needle segmentation. However, the transform is computationally expensive and in the standard form is ineffective for real-time segmentation applications. This paper proposes a dedicated hardware architecture for the Hough transform based on distributed arithmetic (DA) principles that results in a real-time implementation. The architecture exploits the inherent parallelism of the Hough transform and reduces the overall computation time. The DA-Hough transform architecture has been implemented using the Xilinx field-programmable gate array (FPGA). For a 256 x 256-bit image, the proposed design takes between 0.1 ms and 1.2 ms to process the Hough transform when the feature points in the image are varied from 2% to 50% of the total image;these values are well within the bounds of real-time operation and thus can facilitate needle segmentation in real time.

关键词： bit-level arithmetic distributed arithmetic Hough transform

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AN EFFICIENT FREQUENCY DOMAIN INTRA PREDICTION FOR H.264/AVC

AN EFFICIENT FREQUENCY DOMAIN INTRA PREDICTION FOR H.264/AVC

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15th IEEE International Conference on Image Processing (ICIP 2008)

作者： Shaaban, Mohsen Bayoumi, Magdy Univ Louisiana Lafayette Ctr Adv Comp Studies Lafayette LA 70504 USA

ISBN: (纸本)9781424417650

This paper presents an efficient intra prediction implementation for H.264/AVC in the frequency domain. Intra prediction in the frequency domain is vital for transform domain heterogeneous video transcoding in wireless and mobile networks. A limited computation capabilities constraint constitutes a burden over such networks. New distributed intra prediction arithmetic is proposed with only addition and shift operations for transform domain intra prediction modes computations. Compared to previous attempts the proposed method reduces the computations extensively by eliminating the expensive matrix multiplications and omits the need for excessive memory storage.

关键词： Intra Prediction Transform Domain distributed arithmetic H.264/AVC Video Transcoding

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Efficient Implementation of CNC Position Controller using FPGA

Efficient Implementation of CNC Position Controller using FP...

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6th IEEE International Conference on Industrial Informatics

作者： Tao, Yaodong Lin, Hu Hu, Yi Zhang, Xiaohui Wang, Zhicheng Univ Sci & Technol China Hefei 230027 Anhui Peoples R China Chinese Acad Sci Shenyang Inst Comp Technol Natl Engn Res Ctr High End CNC Shenyang 110004 Peoples R China

ISBN: (纸本)9781424421701

In this paper, an efficient design scheme for implementation of the High-speed CNC Position Controller (PC) using Field Programmable Gate Array (FPGA) technology is presented. The algorithm is implemented using a distributed arithmetic (DA)-based scheme where a Look-Up-Table (LUT) mechanism inside the FPGA is utilized. Two novel DA-based CNC Position Controllers have been proposed for FPGA implementation. The implementation results show that the two DA-based PCs use 0.8% and 1.5% logic resource of FPGA device respectively comparing the multiplier-based design uses 51.1% logic resource of FPGA device. These two DA-based designs, using a 32 MHz clock as input this can ensure the servo loop update frequency reaches I MHz to satisfy the high-speed CNC requirement.

关键词： distributed arithmetic position controller servo loop update time FPGA design

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Multiplier-less Floating Point 1D DCT Implementation

Multiplier-less Floating Point 1D DCT Implementation

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IEEE Region 10 Conference (TENCON 2008)

作者： Singh, Gurkirat Kumar, Arun Mishra, Amit Kumar Indian Inst Technol Dept Elect & Commun Engn Gauhati 781039 India

ISBN: (纸本)9781424424085

Multimedia applications are becoming even more demanding. Hence, the next generation codecs invariably should be floating point compliant. With the field programmable gate arrays (FPGAs) technology getting mature, more and more signal processing applications are finding their niche in FPGAs. Current generation FPGAs have got hardware multipliers. However, these are general purpose multipliers and cannot be used for specific purposes. The present paper presents a novel FPGA implementation of one dimensional (8 x 1) point, multiplier less, floating point Discrete Cosine Transform. distributed arithmetic, parallelism and pipelining are exploited to produce a DCT implementation on a single FPGA. Two implementations are presented, one using single LUT and second using 2 parallel LUTs utilizing 68% and 89% area respectively with a maximum clock frequency of around 50MHz.

关键词： FPGAs DCT codecs distributed arithmetic floating point notation

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A micropower programmable DSP using approximate signal processing based on distributed arithmetic

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2004年第2期39卷 337-347页

作者： Amirtharajah, R Chandrakasan, AP Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA MIT Dept Elect Engn & Comp Sci Cambridge MA 02139 USA

A recent trend in low-power design has been the employment of reduced precision processing methods for decreasing arithmetic activity and average power dissipation. Such designs can trade off power and arithmetic precision as system requirements change. This work explores the potential of distributed arithmetic (DA) computation structures for low-power precision-on-demand computation. We present an ultralow-power DSP which uses variable precision arithmetic, low-voltage circuits, and conditional clocks to implement a biomedical detection and classification algorithm using only 560 nW. Low energy consumption enables self-powered operation using ambient mechanical vibrations, converted to electric energy by a MEMS transducer and accompanying power electronics. The MEMS energy scavenging system is estimated to deliver 4.3 to 5.6 muW of power to the DSP load.

关键词： digital signal processing (DSP) distributed arithmetic energy scavenging low power

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FPGA implementation of FIR filter using 2-bit parallel distributed arithmetic

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2004年第5期E87A卷 1280-1282页

作者： Jeng, SS Chang, SM Lan, BS Natl Dong Hwa Univ Dept Elect Engn Hualien Taiwan

An efficient architecture for a FPGA symmetry FIR filter is proposed that employs 2-bit parallel-distributed arithmetic (2-bit PDA). The partial product is pre-calculated and saved into the distributed ROM. This eliminates the large amount of logic needed to compute multiplication results. The proposed architecture consumes less area and offers higher speed operation because the multiplier is omitted.

关键词： distributed arithmetic finite impulse response (FIR)filter

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New distributed arithmetic algorithm for low-power FIR filter implementation

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IEEE SIGNAL PROCESSING LETTERS 2004年第5期11卷 463-466页

作者： Hwang, SY Han, G Kang, SH Kim, J Yonsei Univ Dept Elect & Elect Engn Seoul 120749 South Korea

This letter proposes a new distributed arithmetic (DA) algorithm for low-power finite-impulse response (FIR) filter implementation. The characteristic of the proposed algorithm is that the FIR filters using the proposed algorithm do not need to employ two's complement representation in lookup tables as well as multiply-and -accumulation blocks. Thus, the proposed algorithm can minimize the dynamic power consumption of the FIR filters. The experimental results show that the lowpass FIR filter using the proposed algorithm achieves 29% and 26% power consumption reduction compared to that using the conventional algorithm for zero-mean random inputs and speech inputs, respectively.

关键词： distributed arithmetic lookup table (LUT) low-power finite-impulse response (FIR) filter

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An area efficient high performance DCT distributed architecture for video compression

An area efficient high performance DCT distributed architect...

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9th International Conference on Advanced Communication Technology (ICACT 2007)

作者： Chen, Yanling Cao, Xixin Xie, Qingqing Peng, Chungan Peking Univ Sch Software & Microelect 24 Jin Yuan Rd Daxing Ind Dev Zone Beijing 102600 Peoples R China

ISBN: (纸本)9788955191318

Discrete Cosine Transform ( DCT), which is an important component of image and video compression, is adopted in various standardized coding schemes, such as JPEG MPEGx and H.26x. But when compute a two-dimensional (2D) DCT, a large number of multiplications and additions are required in the direct approach. Multiplications, which are the most time-consuming operations in simple processor, can be completely avoided in the proposed architecture for real-time image compression. An area efficient high performance VLSI architecture for DCT based on the distributed arithmetic is proposed in this paper. Minimum number of additions is used to the DCT by exploiting the timing property of the DCT transform based on the distributed arithmetic. A case study of 8 x 8 DCT architecture based on the DA is analyzed. Savings exceeding 97% are achieved for the DCT implementation.

关键词： distributed arithmetic discrete cosine transform

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