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检索条件"主题词=distributed arithmetic"
221 条 记 录,以下是151-160 订阅
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Coefficient elimination algorithm for low energy distributed arithmetic DCT architectures
Coefficient elimination algorithm for low energy distributed...
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IEEE Workshop on Signal Processing Systems
作者: Darwish, T Bayoumi, M Intel Corp Lafayette LA 70504 USA Univ Louisana Ctr Adv Comp Studies Lafayette LA USA
An energy aware DCT (Discrete Cosine Transform) architecture based on the distributed arithmetic concept is proposed. Architectures based on the distributed arithmetic concept are inherently low power as they are mult... 详细信息
来源: 评论
A distributed arithmetic architecture for fast implementation of vector or matrix products
A distributed arithmetic architecture for fast implementatio...
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12th International Workshop on Systems, Signals and Image Processing
作者: Grigoriadis, G Boutalis, Y Mertzios, B Democritus Univ Thrace Dept Elect & Comp Engn GR-67100 Xanthi Greece
Fast implementations of the inner product of two (nxl) vectors, of the (nxn) MVM (matrix vector multiplication) operation and (nxn) MMM (matrix matrix multiplication) operation are of paramount importance in many rese... 详细信息
来源: 评论
A distributed arithmetic hardware architecture for real-time Hough-transform-based segmentation
A distributed arithmetic hardware architecture for real-time...
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18th IEEE Canadian Conference on Electrical and Computer Engineering
作者: Mayasandra, K Salehi, S Wang, W Ladak, HM Univ Western Ontario Dept Elect & Comp Engn London ON N6A 5B9 Canada Univ Western Ontario Dept Med Biophys London ON N6A 3K7 Canada Indiana Univ Purdue Univ Dept Elect & Comp Engn Indianapolis IN USA
Real-time segmentation and tracking of biopsy needles is a very important part of image-guided surgery. Since the needle appears as a straight line in medical images, the Hough transform for straight-line detection is... 详细信息
来源: 评论
AN EFFICIENT FREQUENCY DOMAIN INTRA PREDICTION FOR H.264/AVC
AN EFFICIENT FREQUENCY DOMAIN INTRA PREDICTION FOR H.264/AVC
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15th IEEE International Conference on Image Processing (ICIP 2008)
作者: Shaaban, Mohsen Bayoumi, Magdy Univ Louisiana Lafayette Ctr Adv Comp Studies Lafayette LA 70504 USA
This paper presents an efficient intra prediction implementation for H.264/AVC in the frequency domain. Intra prediction in the frequency domain is vital for transform domain heterogeneous video transcoding in wireles... 详细信息
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Efficient Implementation of CNC Position Controller using FPGA
Efficient Implementation of CNC Position Controller using FP...
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6th IEEE International Conference on Industrial Informatics
作者: Tao, Yaodong Lin, Hu Hu, Yi Zhang, Xiaohui Wang, Zhicheng Univ Sci & Technol China Hefei 230027 Anhui Peoples R China Chinese Acad Sci Shenyang Inst Comp Technol Natl Engn Res Ctr High End CNC Shenyang 110004 Peoples R China
In this paper, an efficient design scheme for implementation of the High-speed CNC Position Controller (PC) using Field Programmable Gate Array (FPGA) technology is presented. The algorithm is implemented using a Dist... 详细信息
来源: 评论
Multiplier-less Floating Point 1D DCT Implementation
Multiplier-less Floating Point 1D DCT Implementation
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IEEE Region 10 Conference (TENCON 2008)
作者: Singh, Gurkirat Kumar, Arun Mishra, Amit Kumar Indian Inst Technol Dept Elect & Commun Engn Gauhati 781039 India
Multimedia applications are becoming even more demanding. Hence, the next generation codecs invariably should be floating point compliant. With the field programmable gate arrays (FPGAs) technology getting mature, mor... 详细信息
来源: 评论
A micropower programmable DSP using approximate signal processing based on distributed arithmetic
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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2004年 第2期39卷 337-347页
作者: Amirtharajah, R Chandrakasan, AP Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA MIT Dept Elect Engn & Comp Sci Cambridge MA 02139 USA
A recent trend in low-power design has been the employment of reduced precision processing methods for decreasing arithmetic activity and average power dissipation. Such designs can trade off power and arithmetic prec... 详细信息
来源: 评论
FPGA implementation of FIR filter using 2-bit parallel distributed arithmetic
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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2004年 第5期E87A卷 1280-1282页
作者: Jeng, SS Chang, SM Lan, BS Natl Dong Hwa Univ Dept Elect Engn Hualien Taiwan
An efficient architecture for a FPGA symmetry FIR filter is proposed that employs 2-bit parallel-distributed arithmetic (2-bit PDA). The partial product is pre-calculated and saved into the distributed ROM. This elimi... 详细信息
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New distributed arithmetic algorithm for low-power FIR filter implementation
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IEEE SIGNAL PROCESSING LETTERS 2004年 第5期11卷 463-466页
作者: Hwang, SY Han, G Kang, SH Kim, J Yonsei Univ Dept Elect & Elect Engn Seoul 120749 South Korea
This letter proposes a new distributed arithmetic (DA) algorithm for low-power finite-impulse response (FIR) filter implementation. The characteristic of the proposed algorithm is that the FIR filters using the propos... 详细信息
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An area efficient high performance DCT distributed architecture for video compression
An area efficient high performance DCT distributed architect...
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9th International Conference on Advanced Communication Technology (ICACT 2007)
作者: Chen, Yanling Cao, Xixin Xie, Qingqing Peng, Chungan Peking Univ Sch Software & Microelect 24 Jin Yuan Rd Daxing Ind Dev Zone Beijing 102600 Peoples R China
Discrete Cosine Transform ( DCT), which is an important component of image and video compression, is adopted in various standardized coding schemes, such as JPEG MPEGx and H.26x. But when compute a two-dimensional (2D... 详细信息
来源: 评论