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High speed low area OBC DA based decimation filter for hearing aids application

INTERNATIONAL JOURNAL OF SPEECH TECHNOLOGY 2020年第1期23卷 111-121页

作者： NagaJyothi, Grande Sridevi, Sriadibhatla VIT Univ Vellore Tamil Nadu India

This brief presents a decimation filter for hearing aid application using distributed arithmetic (DA) approach. In this paper, we propose a reconfigurable offset-binary code (OBC) DA based finite impulse response (FIR) filter with a shared look-up table (LUT) updating scheme. The size of the LUTs in DA increases exponentially with the order of filters. Shared LUT based DA structure is a solution to reduce this large memory requirement for higher order filters. The proposed shared LUT updating scheme uses LUT partitioning in which coefficients are spilt into small length vectors and it ensures a drastic reduction in the size of LUTs. The proposed DA filter is synthesized on CMOS 90 nm technology using Synapsis ASIC Design Compiler. The proposed design achieves high speed at a reduced area-delay product (ADP) when compared with recent designs. The proposed architecture is implemented and tested on Virtex 5vsx95-1ff1136 FPGA and the results show that the proposed design involves less number of slices and offers high speed than existing designs. A three-stage decimation filter of hearing aids is designed with the proposed FIR filter and is implemented on the target device by Matlab simulink and Xilinx system generator.

关键词： distributed arithmetic Decimation filter Hearing aid Look-up-table (LUT) Offset binary code Reconfigurable FIR filter Speech signal

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Low-cost multi-standard video transform core using time-distribution scheme

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ELECTRONICS LETTERS 2016年第24期52卷 1980-1981页

作者： Chen, Y. -H. Tseng, Y. -H. Chang Gung Univ Dept Elect Engn Taoyuan Taiwan Chang Gung Univ Ctr Reliabil Sci & Technol Taoyuan Taiwan Natl Tsing Hua Univ Dept Engn & Syst Sci Hsinchu Taiwan Chang Gung Mem Hosp LinKou Dept Radiat Oncol Taoyuan Taiwan

Cost-effective two-dimensional (2D) discrete cosine transform (DCT) and inverse DCT architectures capable of supporting multiple standards of MPEG, H.264 and VC-1 are presented. The proposed core utilises a 1D core and a transposed memory to achieve a low cost design. Multi-level factor share is implemented in conjunction with distributed arithmetic in a system to enable the sharing of the coefficient matrix circuit in order to reduce hardware costs. The proposed approach employs a time-distribution scheme to enable the simultaneous processing of the first and second dimensions to enhance throughput. A high efficiency of this approach was verified by fabricating a test chip using the TSMC 0.18 mu m CMOS process. The architecture has an operating frequency of 200 MHz, and throughput of 800 M-pixels/s with a gate count of 44.5 K.

关键词： distributed arithmetic discrete cosine transforms inverse transforms video coding CMOS integrated circuits

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A methodology for implementing decimator FIR filters on FPGA

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2013年第12期67卷 993-1004页

作者： Harize, Saliha Benouaret, Mohamed Doghmane, Noureddine Badji Mokhtar Univ Fac Engn Sci Annaba Algeria

This paper presents a methodology which can be used to implement any decimator symmetric/antisymmetric (S/A) finite impulse response (FIR) filter. Two varieties are developed: a classic distributed arithmetic (CDA) based and a modified distributed arithmetic (MDA) based one. Both exploit the polyphase structure and the symmetry/antisymmetry of the filter and are evaluated in terms of area efficiency, speed and power consumption. The choice of the algorithm depends on the performance metrics targeted. The methodology has been applied to implement the filter bank CDF9/7 which constitutes a one dimensional (1D) and one level discrete wavelet transform (DWT). The filter bank also known as the bior4.4 biorthogonal wavelets is recommended by the JPEG2000 standard for lossy compression of images and video. The architecture has been implemented on an Altera field programmable gate array (FPGA) and the simulations run in Matlab, Modelsim and Altera Quartus II. The results prove the efficiency of the algorithms and show the tradeoff between the area occupied, the throughput and the power consumption. (C) 2013 Elsevier GmbH. All rights reserved.

关键词： distributed arithmetic FIR filter FPGA Look up table (LUT) Polyphase structure

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Analysis and synthesis of weighted-sum functions

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2005年第5期25卷 789-796页

作者： Sasao, T Kyushu Inst Technol Dept Comp Sci & Engn Iizuka Fukuoka 8208502 Japan

A weighted-sum (WS) function computes the sum of selected integers. This paper considers a design method for WS functions by look-up table (LUT) cascades. In particular, it derives upper bounds on the column multiplicities of decomposition charts for WS functions. From these, the size of LUT cascades that realize WS functions can be estimated. The arithmetic decomposition of a WS function is also shown. With this method, a WS function can be implemented with cascades and adders.

关键词： binary decision diagram column multiplicity complexity of logic functions digital filter distributed arithmetic field programmable gate array (FPGA) functional decomposition LUT cascades radix converter symmetric function threshold function

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Implementation of efficient reconfigurable FIR filter with control logic for 5G applications

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SOFT COMPUTING 2021年第15期25卷 10509-10518页

作者： Raju Kalidindi, S. N. Terlapu, Sudheer Kumar Krishna, M. Vamshi Centurion Univ Technol & Management R Sitapur 761211 Odisha India Shri Vishnu Engn Coll Women Bhimavaram 534202 India Dhanekula Inst Engn & Technol Vijayawada 521151 India

Filters are used to achieve frequency selectivity on the spectrum of input signal. Due to the stability of finite impulse response (FIR) filters, they are used in most of the applications. In the conventional FIR filters, the frequency band is fixed and cannot be changed once it is designed. Hence, there is a necessity of an FIR filter with auto-adjustment of band width in modern day communication systems like 5G. The design of FIR filter requires more number of filter coefficients to get the desired bandwidth specification. This results in a large slice for field programmable gate array implementation. Here, it proposed a state machine to select different FIR filters with the designated set of coefficients. Each FIR filter is having different set of coefficients, and based on the frequency of the clock signal, the FIR filter is selected and thereby frequency selectivity can be achieved. The proposed method is to implement reconfigurable FIR (RFIR) filter with control logic for auto-adjustment of frequency selections to achieve better band width requirements. The filter order is initially selected as 4 and presented the simulation results. The order of the filter(n) increased to 24 for verifying the bandwidth selection. The proposed architecture is compared with the existing architecture with 16 bits and 11 taps. The proposed method saves 33.5% of look-up-tables (LUTs) compared to the existing methods. Simulation results presented are verified using Xilinx ISE design suite 14.7. The total number of four-input LUTs utilized are 630 for order(n) of the filter 24. Power consumed by the overall design is 195 mW.

关键词： Coefficient selection distributed arithmetic FIR Filter design Folded direct form Multiply and accumulate Unfolded direct Form

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A 3.5pJ/bit 8-tap-Feed-Forward 8-tap-Decision Feedback Digital Equalizer for 16Gb/s I/Os 40

A 3.5pJ/bit 8-tap-Feed-Forward 8-tap-Decision Feedback Digit...

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40th European Solid-State Circuit Conference (ESSCIRC)

作者： Toifl, Thomas Buchmann, Peter Beukema, Troy Beakes, Michael Braendli, Matthias Francese, Pier Andrea Menolfi, Christian Kossel, Marcel Kull, Lukas Morf, Thomas IBM Res GmbH IBM Zurich Res Lab CH-8803 Ruschlikon Switzerland IBM Corp Div Res Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)9781479956968

In this paper, we present a digital equalizer for 16Gb/s backplane I/Os which consumes only 3.5pJ/bit for an 8-tap FFE and 4+4 tap DFE operation. Several design choices were chosen to enable low power consumption at high speed. First, the FFE leverages parallelism to lower the supply voltage, while the DFE runs from a higher supply to close the feedback loop. Second, the FFE uses distributed arithmetic to reduce the number of required additions. Third, the DFE taps leave a window of four equalizer taps, which are covered by the FFE, in order to close the timing. Finally, a custom digital design style was chosen, which enabled the optimization of critical blocks and wires. At 0.6V supply, the FFE was measured to consume 1pJ/bit, while the DFE consumes 1.6pJ/bit at 0.9V while running at 16Gb/s.

关键词： digital I/Os backplane DSP FFE DFE DA distributed arithmetic low-power

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A High Speed FPGA Implementation of the 2D DCT for Ultra High Definition Video Coding

A High Speed FPGA Implementation of the 2D DCT for Ultra Hig...

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18th International Conference on Digital Signal Processing (DSP)

作者： Kitsos, Paris Voros, Nikolaos S. Dagiuklas, Tasos Skodras, Athanassios N. Branch Nafpaktos Technol Educ Inst Messolonghi Dept Telecommun Syst & Networks Nafpaktos Greece Hellenic Open Univ Dept Comp Sci Patras Greece Univ Patras Dept Elect & Comp Engn Patras Greece

ISBN: (纸本)9781467358057

This paper presents two high performance FPGA architectures for the 2D DCT computation for Ultra High Definition video coding systems. Both architectures use distributed arithmetic to perform the necessary multiplications instead of traditional multipliers. The first architecture uses 105 clock cycles to transform an 8x8 block and reaches a rate of up to 206 samples per second at a 338.5 MHz frequency, while the second one requires 65 cycles for each 8x8 block and achieves a rate equal to 252 samples per second at 256 MHz. Both architectures have been implemented using VHDL. Virtex7 FPGA of Xilinx has been used for the realization of both implementations.

关键词： Video Coding 2D DCT distributed arithmetic FPGA Implementation VHDL

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MSDCT architecture implementation with DA based optimized LUT

MSDCT architecture implementation with DA based optimized LU...

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6th World Congress on Intelligent Control and Automation

作者： Kamran, Muhammad Shi, Feng Ji, Weixing Beijing Inst Technol Dept Comp Sci & Engn Beijing 100081 Peoples R China

ISBN: (纸本)1424403316

In this paper a modified scaled discrete cosine transform hardware implementation is presented which will be further utilized in video chip application. The hardware design is based on the description of the algorithm along with the proof of operational steps to complete inner product operation required for DCT application. This paper highlights and compares 8X8 pixels block DCT architecture of conventional design with our optimized design. Optimized hardware is presented by virtue of distributed arithmetic (DA) and contains multiplications based on Computational Sharing Multiplier (CSHM) concept. DA is utilized for LUT size optimization which helps to keep the area of chip and complexity of connections reasonably small.

关键词： MSDCT distributed arithmetic CSHM LUT optimization

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A circular formulation of the prime length DHT kernel and its FPGA implementation 4

A circular formulation of the prime length DHT kernel and it...

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Joint Conference of the 4th International Conference on Information, Communications and Signal Processing/4th Pacific-Rim Conference on Multimedia (ICICS-PCM 2003)

作者： Srikanthan, T Kumar, N Jhavar, A Nanyang Technol Univ Ctr High Performance Embedded Syst Singapore 639798 Singapore

ISBN: (纸本)0780381858

This paper presents a FPGA implementation of a one-dimensional prime-length Discrete Hartley Transform. The architecture for the hardware realization has been formulated to ensure maximum area and time efficiency. The presented design exploits the advantages presented by the distributed arithmetic and Circular Formulation Techniques. distributed arithmetic is very useful in creating efficient FPGA implementations while cyclic convolution provides the advantages of high computing parallelism, and low computation complexity. A single FPGA has been used to provide an area efficient design with a sampling rate of 12.5 Million samples per second. The results indicate comparable speeds to that of the DCT.

关键词： Discret Hartley Transform FPGA distributed arithmetic circular convolution

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Discrete wavelet transform IPcore design for image compression

Discrete wavelet transform IPcore design for image compressi...

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7th International Conference on Signal Processing

作者： Fu, WH Meng, LM Wang, XY Zhejiang Prov. Key Lab. Opt. F.C.T. Zhejiang University of Technology China Eastern Communications Co. Ltd.

ISBN: (纸本)7121002159

Discrete wavelet transform (DWT), which is recently used by some international standard organizations in image compression protocols, has an excellent performance on multiresolution representation. Because of DWT's computation-intensive nature. however, it seldom meets the application of real-time video system. Field programmable gate array (FPGA) has the advantages as parallel. high-speed, and easy-modify. These merits make FPGA the appropriate choice for the DWT implementations. This paper describes an IPcore design based on hardware describe language (HDL), and implemented on FPGA device. The core uses distributed arithmetic. parallel operating, and pipelining design. In addition, IPcore technology protects and encapsulates the design of image compression core.

关键词： wavelet image compression IPcore. FPGA distributed arithmetic

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