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A Hardware Implementation of Discrete Wavelet Transform for Compression of a Natural Image

A Hardware Implementation of Discrete Wavelet Transform for ...

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International Conference on Algorithms, Methodology, Models and Applications in Emerging Technologies (ICAMMAET)

作者： Padmavati, S. Meshram, Vaibhav Jayadevappa Jain Univ ECE Dept Bengaluru India Dayananda Sagar Univ ECE Dept Bengaluru India JSSATE B Campus Instrumentat Dept Bengaluru India

ISBN: (纸本)9781509033782

Digital images can be represented in different forms/representations by using Image Transforms, which are simple or complex mathematical operations on the image. These transforms finds application in compression, enhancement, pattern recognition, and feature extraction etc. Discrete Wavelet Transform (DWT) is a widely used wavelet transformation. DWT transforms image from space domain to frequency domain, where the wavelets are discretely sampled. DWT has various advantages over other image transforms such as image can be represented in multi resolution form, avoids the division of image into non-overlapping blocks, blocking artifacts are avoided to achieve a high compression ratio, better identification of data suitable for human perception, provides better localization in spatial and frequency domain. DWT implemented on software [Matlab] usually has lower throughput, which is due to high overall design cycle time. This can be improved through hardware implementation of DWT. In this paper an effective high speed DWT architecture has been designed using distributed arithmetic (DA) concept. The designed architecture has been simulated and synthesized by using Verilog HDL for the selected device ZYNQZC706 (7z045ffg900-2). Our implementation is validated on a natural image of dimension 512*512. This implementation reduces the overall design cycle time to 0.670 nanoseconds.

关键词： Image Processing Image Compression DWT FPGA Implementation distributed arithmetic

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An Efficient VLSI Architecture for Discrete Hadamard Transform 29

An Efficient VLSI Architecture for Discrete Hadamard Transfo...

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29th International Conference on VLSI DESIGN / 15th International Conference on Embedded Systems (VLSID)

作者： Basiri, Mohamed Asan M. Mahammad, Noor S. K. Indian Inst Informat Technol Design & Mfg Kanchee Dept Comp Sci & Engn Madras 600127 Tamil Nadu India

ISBN: (纸本)9781467387002

This paper proposes an efficient VLSI architecture for discrete Hadamard transform, which is used in real time digital signal processing applications like image coding, MPEG, and CDMA etc. The proposed N-point Hadamard transform architecture consists of signed carry save adder tree. So the depth of the architecture falls within the bounds of O(log(2) N). The same proposed architecture is implemented for 2D-discrete Hadamard transform, where the hardware utilization is full. In other words, row/column processing of 2D-transform is carried with same 1D-hardware. The performance results show that the proposed architecture gives better performance compared with existing architectures using 45 nm CMOS TSMC library. The proposed 8-point 1D-DHT achieves an improvement of 55.14% and 42.07% in worst path delay over conventional and linear systolic array based 1D-DHT architectures respectively. Similarly proposed 8 x 8-point 2D-DHT achieves an improvement of 50.7%, 21.7%, and 51.1% in worst path delay over conventional, linear systolic array, and distributed arithmetic based 2D-DHT architectures respectively.

关键词： distributed arithmetic DSP processor Hadamard Transform

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VLSI Architecture Design of 9/7 Discrete Wavelet Transform for Image Processing 62

VLSI Architecture Design of 9/7 Discrete Wavelet Transform f...

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62nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Javed, Sadaf Younis, Ch. Jabbar Alam, Mehboob Massoud, Yehia Mirpur Univ Sci & Technol Dept Elect Engn Mirpur 10250 Ajk Pakistan Stevens Inst Technol Sch Syst & Enterprises Hoboken NJ 07030 USA

ISBN: (纸本)9781728127880

In image processing, transform coding de-correlates images to pre-condition them for efficient compression. In this work, we propose VLSI architecture design of a hardware-efficient 9/7 Discrete Wavelet Transform (DWT). The architecture takes advantage of Canonical Signed Digit (CSD) and distributed arithmetic (DA) to represent and optimally distribute co-efficients to reduce the number of adder and shift registers. In addition, the co-efficient multiplication also exploits the horizontal and vertical redundancy in the architecture to reduce the hardware computational complexity. The result is a filter-based design, exploiting hardware path of architecture using CSD coefficients, which finds minimum realization. The proposed architecture is simulated using Verilog Hardware Description Language (HDL). A comparison with other architectures of 9/7 DWT shows a 18.75% reduction in hardware. The result is a hardware-efficient architecture, which provides a low-power solution for image and signal processing applications.

关键词： Discrete Wavelet Transform VLSI distributed arithmetic Image Processing Canonical Signed Digit

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Low Area & Memory Efficient VLSI Architecture Of 1D/2D DWT For Real Time Image Decomposition 8

Low Area & Memory Efficient VLSI Architecture Of 1D/2D DWT F...

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8th IEEE International Symposium on Embedded Computing and System Design (ISED)

作者： Chakraborty, Anirban Banerjee, Ayan Indian Inst Engn Sci & Technol Dept Elect & Telecommun Engn Sibpur Howrah India

ISBN: (纸本)9781538665756

There is a dearth of high quality reconfigurable hardware for DWT which can be extensively used in various real time signal and image processing applications. In this article, we have focused on proposing a dedicated customizable hardware for DWT applicable to 1D/2D signal processing. We have proposed bit-serial distributed arithmetic (DA) based VLSI architectures for 1D/2D DWT. Exploitation of DA enables us to make our designs Multiplierless, thereby consuming less area. Bit serial configuration of DA is also exploited to introduce modularity and pipelining in the proposed convolution DWT based 1D/2D architectures. Though the speed of the proposed designs may not be suitable for certain applications, a number of parallel channels can be introduced for the same. The provision of mode selection can efficiently be used to realize 9/7 and also 5/3 DWT filters in the same proposed architecture. In the proposed 1D/2D architecture, we have achieved about 50% memory size reduction, 30% reduction in area consumption and comparable speed in comparison to the other latest notable DWT architecture so far. We have verified the viability of our proposed 2D architecture by utilizing it in real time image decomposition.

关键词： DWT distributed arithmetic multiplierless image decomposition image enhancement

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A Design of VB-DDC using DA-based Systolic FIR Filter

A Design of VB-DDC using DA-based Systolic FIR Filter

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3rd International Conference on Mechanical and Electronics Engineering (ICMEE 2011)

作者： Xu Ping Xia Wei He Zishu Univ Elect Sci & Technol China Sch Elect Engn Chengdu 610054 Peoples R China

ISBN: (纸本)9783037852866

In this paper, we present yet another design of the variable-bandwidth digital down-converter (VB-DDC). The shaping filter in the DDC architecture is substitute with a method which is implemented with fully pipelined computing structure of systolic decomposition for distributed arithmetic (DA) based FIR filer. The systolic structure of the FIR filter involves significantly less memory and complexity compared with the existing ones. The effectiveness of the design is validated by the proposed FPGA implementation results.

关键词： digital down-converter distributed arithmetic systolic finite-impulse-response filer

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DA-FBLMS Adaptive Filter Design for Accurate ECG Signal Detection using FPGA 58

DA-FBLMS Adaptive Filter Design for Accurate ECG Signal Dete...

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58th International Scientific Conference on Information, Communication and Energy Systems and Technologies (ICEST)

作者： Antonov, Svetlin Dembrani, Mahesh Patil, Dipak Jaware, Tushar Badgujar, Ravindra Tech Univ Sofia Fac Telecommun Sofia Bulgaria R C Patel Inst Technol Fac Elect & Telecommun Engn Shirpur Maharashtra India Sandip Inst Engn & Management Fac Elect & Telecommun Engn Nasik India

ISBN: (纸本)9798350310733

Accurate identification of electrocardiogram (ECG) signals is crucial in clinical diagnostics. This research paper presents an implementation of an adaptive digital filter for reliable ECG signal identification. The study focuses on utilizing the distributed arithmetic (DA) and Fast Block LMS (FBLMS) algorithm to enhance accuracy and reduce power consumption. To achieve optimal clutter elimination and convergence speed, adaptive step size algorithms based on correlation coherence measurements of the reference signal are employed. The implementation is carried out on FPGA Virtex 5 boards, emphasizing minimal power and memory requirements. Experimental results demonstrate improved accuracy and reduced power consumption, indicating the potential of the proposed approach for reliable ECG signal identification.

关键词： distributed arithmetic BLMS DA-BLMS DA-FBLMS ECG FPGA

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Multiplier-less Floating Point 1D DCT Implementation

Multiplier-less Floating Point 1D DCT Implementation

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IEEE Region 10 Conference (TENCON 2008)

作者： Singh, Gurkirat Kumar, Arun Mishra, Amit Kumar Indian Inst Technol Dept Elect & Commun Engn Gauhati 781039 India

ISBN: (纸本)9781424424085

Multimedia applications are becoming even more demanding. Hence, the next generation codecs invariably should be floating point compliant. With the field programmable gate arrays (FPGAs) technology getting mature, more and more signal processing applications are finding their niche in FPGAs. Current generation FPGAs have got hardware multipliers. However, these are general purpose multipliers and cannot be used for specific purposes. The present paper presents a novel FPGA implementation of one dimensional (8 x 1) point, multiplier less, floating point Discrete Cosine Transform. distributed arithmetic, parallelism and pipelining are exploited to produce a DCT implementation on a single FPGA. Two implementations are presented, one using single LUT and second using 2 parallel LUTs utilizing 68% and 89% area respectively with a maximum clock frequency of around 50MHz.

关键词： FPGAs DCT codecs distributed arithmetic floating point notation

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Implementation of 2D-DCT on XC4000 series FPGA using DFT-based DSFG and DA architectures

Implementation of 2D-DCT on XC4000 series FPGA using DFT-bas...

引用

International Conference on Image Processing (ICIP 2001)

作者： Kiryukhin, G Celenk, M Ohio Univ Stocker Ctr Sch Elect Engn & Comp Sci Athens OH 45701 USA

ISBN: (纸本)0780367251

In many multimedia applications, image processing tools require very high speed implementation of two dimensional (2D) discrete cosine transform (DCT) In this paper, two 2D-DCT architectures were realized based on the decomposition of 2D -DCT into two one-dimensional (11)) DCT's Each of the resultant ID-DCT's was implemented using a flo -graph (FG) representation of the real part of the Fourier transform for the first architecture and the distributed arithmetic (DA) for the second architecture, respectively Error simulation was performed for different data word lengths, and average and maximum absolute errors were calculated for both architectures fo several possible worst cases Based on the simulation results, the correct word sizes were determined for both implementations By describing the FG architecture in VHDL and implementing it in the Xilinx XC4000 series FPGA chip, our results showed that the proposed technique utilized less combinational logic blocks (CLB's) as compared to the FG realization in [2] and at the same time provided performance increase of up to 28% (190Mpix/sec).

关键词： 2D-DCT FPGA implementation distributed arithmetic flo -graph architecture

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A HARDWARE-EFFICIENT IMPLEMENTATION OF THE FAST AFFINE PROJECTION ALGORITHM

A HARDWARE-EFFICIENT IMPLEMENTATION OF THE FAST AFFINE PROJE...

引用

IEEE International Conference on Acoustics, Speech and Signal Processing

作者： Lo, Haw-Jing Anderson, David V. Georgia Inst Technol Sch Elect & Comp Engn Ctr Signal & Image Proc Atlanta GA 30332 USA

ISBN: (纸本)9781424423538

This paper presents a high-throughput, low-latency, hardware-efficient fixed-point implementation of the fast affine projection (FAP) algorithm. The proposed architecture utilizes reusable distributed arithmetic (RDA) in combination with optimizations in the update process to enable the coefficients to be updated in a fixed number of cycles independent of filter length. Fixed-point simulations show that the effect of replacing some of the multiplications with arithmetic shifts is minor, with RDA-FAP maintaining a faster convergence rate than NLMS. The proposed design is also compared against a multiplier-based design in terms of number of computations and number of clock cycles needed for a single FAP update cycle.

关键词： distributed arithmetic adaptive filters fast affine projection

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An Optimized Design for a Decimation Filter and Implementation for Sigma-Delta ADC

An Optimized Design for a Decimation Filter and Implementati...

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IEEE International Conference of Electron Devices and Solid-State Circuits

作者： Cui, Yingying Huang, Jie Wu, Lingjuan Cui, Xiaoxin Yu, Dunshan Peking Univ Inst Microelect Beijing 100871 Peoples R China

ISBN: (纸本)9781424442973

The area, speed and power consumption of over-sampled data converters are governed largely by the decimation filters in Sigma-Delta Analog/Digital converters(ADC) and multiplication is the core operation of the digital filter, so the performance of digital system is determined by multiplication. This paper compares four different popular methods: Conventional multiplications and additions;full custom distributed arithmetic (DA) scheme;Add-and-Shift method with CSD encoding;advanced sub-expression sharing algorithm. Each scheme is analyzed in detail including implementing process and the experimental results are given to evaluate each scheme. All of these implementations are aimed to implement using Design Compiler. Then this paper presents an optimized circuit for the decimation filter and the decimation filter for Sigma-Delta ADC is implemented using 0.35 mu m CMOS technology, with an approximate silicon area of 19mm(21).

关键词： sigma-delta ADC CSD encoding distributed arithmetic decimation filter

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