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检索条件"主题词=distributed arithmetic"

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An Optimized Design for a Decimation Filter and Implementation for Sigma-Delta ADC

An Optimized Design for a Decimation Filter and Implementati...

引用

IEEE International Conference of Electron Devices and Solid-State Circuits

作者： Cui, Yingying Huang, Jie Wu, Lingjuan Cui, Xiaoxin Yu, Dunshan Peking Univ Inst Microelect Beijing 100871 Peoples R China

ISBN: (纸本)9781424442973

The area, speed and power consumption of over-sampled data converters are governed largely by the decimation filters in Sigma-Delta Analog/Digital converters(ADC) and multiplication is the core operation of the digital filter, so the performance of digital system is determined by multiplication. This paper compares four different popular methods: Conventional multiplications and additions;full custom distributed arithmetic (DA) scheme;Add-and-Shift method with CSD encoding;advanced sub-expression sharing algorithm. Each scheme is analyzed in detail including implementing process and the experimental results are given to evaluate each scheme. All of these implementations are aimed to implement using Design Compiler. Then this paper presents an optimized circuit for the decimation filter and the decimation filter for Sigma-Delta ADC is implemented using 0.35 mu m CMOS technology, with an approximate silicon area of 19mm(21).

关键词： sigma-delta ADC CSD encoding distributed arithmetic decimation filter

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Efficient color space conversion using custom instruction in a RISC processor

Efficient color space conversion using custom instruction in...

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IEEE International Symposium on Circuits and Systems

作者： Bilal, Muhammad Masud, Shahid Lahore Univ Management Sci Dept Comp Sci & Engn Lahore 54792 Pakistan

ISBN: (纸本)9781424409204

A new architecture for color space conversion in RGB to YCbCr domain has been proposed. The architecture exploits the similarity in bit-planes of a natural image to bring the algorithmic efficiency of distributed arithmetic (DA) approach close to that of a full multiplier design. Modifications have been carried out in DA to further reduce the computational complexity by a factor of two for most natural images. The color space conversion architecture has been incorporated in OR1200 open source IP processor core to provide custom instruction. Simulation and synthesis results on Xilinx FPGA are provided.

关键词： color space bit-planes distributed arithmetic instruction set extension RISC processor

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DA-FBLMS Adaptive Filter Design for Accurate ECG Signal Detection using FPGA 58

DA-FBLMS Adaptive Filter Design for Accurate ECG Signal Dete...

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58th International Scientific Conference on Information, Communication and Energy Systems and Technologies (ICEST)

作者： Antonov, Svetlin Dembrani, Mahesh Patil, Dipak Jaware, Tushar Badgujar, Ravindra Tech Univ Sofia Fac Telecommun Sofia Bulgaria R C Patel Inst Technol Fac Elect & Telecommun Engn Shirpur Maharashtra India Sandip Inst Engn & Management Fac Elect & Telecommun Engn Nasik India

ISBN: (纸本)9798350310733

Accurate identification of electrocardiogram (ECG) signals is crucial in clinical diagnostics. This research paper presents an implementation of an adaptive digital filter for reliable ECG signal identification. The study focuses on utilizing the distributed arithmetic (DA) and Fast Block LMS (FBLMS) algorithm to enhance accuracy and reduce power consumption. To achieve optimal clutter elimination and convergence speed, adaptive step size algorithms based on correlation coherence measurements of the reference signal are employed. The implementation is carried out on FPGA Virtex 5 boards, emphasizing minimal power and memory requirements. Experimental results demonstrate improved accuracy and reduced power consumption, indicating the potential of the proposed approach for reliable ECG signal identification.

关键词： distributed arithmetic BLMS DA-BLMS DA-FBLMS ECG FPGA

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Implementation of two dimensional forward DCT and inverse DCT using FPGA

Implementation of two dimensional forward DCT and inverse DC...

引用

10th International IEEE Tencon Conference

作者： Mohd-Yusof, Z Suleiman, I Aspar, Z Univ Technol Malaysia Fac Elect Engn Johor Bahru Johor Malaysia

ISBN: (纸本)0780363558

This paper describes the (field programmable gate array) FPGA implementation of two dimensional forward and inverse Discrete Cosine Transform (2D-DCT and 2D-IDCT) using the 100K gate ALTERA FLEX10K100 FPGA/CPLD. The architecture used in both 2D-DCT and 2D-IDCT is based on the conventional row-column decomposition method. The use of Fast algorithm and distributed arithmetic (DA) technique to implement the DCT and IDCT greatly reduces the hardware complexity.

关键词： DCT/IDCT image compression distributed arithmetic FPGA/CPLD

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A flexible design of filterbank architectures for discrete wavelet transforms

A flexible design of filterbank architectures for discrete w...

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32nd IEEE International Conference on Acoustics, Speech and Signal Processing

作者： Longa, Patrick Miri, Ali Bolic, Miodrag Univ Ottawa Sch Informat Technol & Engn Ottawa ON K1N 6N5 Canada

ISBN: (纸本)1424407281

In this paper, distributed arithmetic (DA) has been used to implement a fully parallel LUT-based DA wavelet filterbank with interlaced input registers. In our scheme, decimation has been seamlessly integrated into the filter structure to achieve the same throughput performance as polyphase-based filterbanks. However, because partitioning of the filters is avoided, our scheme gives more flexibility to implement the LUT-DA structure, and consequently, lets designers maximize area utilization on LUT-based FPGAs. Our architecture has been designed for orthonormal and biorthogonal wavelets, and implemented on an Altera Stratix II FPGA. Significant reduction in terms of area requirements and increased throughput performance are achieved when compared to other DWT filterbanks based on DA, convolution or the lifting scheme.

关键词： wavelet transforms distributed arithmetic field programmable gate arrays

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Self-configurable digital controllers for smart structural systems using FPGAs

Self-configurable digital controllers for smart structural s...

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Smart Structures and Materials 2002 Conference

作者： Satagopan, VR Rao, VS Mitchell, K Pottinger, H Univ Missouri Dept Elect & Comp Engn Intelligent Syst Ctr Rolla MO 65401 USA

ISBN: (纸本)0819444480

Smart structural systems require control systems, which are integrated into structures, to be small, light weight and power-efficient. Re-configurable digital signal processing using Field Programmable Gate Arrays (FPGAs) is now preferred over Digital Signal Processors (DSPs) and Application Specific Integrated Circuits (ASICs) for high performance applications. The FPGAs, due to their re-programmable and dynamic nature, are more suitable in developing hardware implementations because several configurations can be tested and experimented easily without any additional hardware cost. Being small, lightweight and power-efficient, FPGAs are one of the best platforms for building controllers for smart structures. distributed arithmetic is a widely used technique for hardware efficient implementations of inner product between a fixed and a variable data vectors. The computational requirements of smart structural controller match this type very well. The objective of the research is to design easily configurable stand-alone smart controller, which could be used for real-time control applications. Self-configurable controllers are implemented and tested on a cantilevered beam.

关键词： smart controller self-configurable system re-configurable distributed arithmetic FPGA

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A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters

A Dynamically Reconfigurable Platform for Fixed-Point FIR Fi...

引用

International Conference on Reconfigurable Computing and FPGAs

作者： Llamocca, Daniel Pattichis, Marios Vera, G. Alonzo Univ New Mexico Dept Elect & Comp Engn Albuquerque NM 87131 USA Microelect Res & Dev Corp Albuquerque NM USA

ISBN: (纸本)9781424452934

Many DSP, image and video processing applications use Finite Impulse Response (FIR) filters as basic computing blocks. Our paper introduces an efficient dynamically reconfigurable FIR system that can adapt the number of filter coefficients, and their values, in real time. Here, dynamic reconfiguration is used to switch between different, pre-computed, fixed-point realizations of different digital filters. Our platform relies on the use of distributed arithmetic blocks, mapped to the specific LUTs of the underlying FPGA. Dynamic reconfiguration of the coefficients is limited to changing a small number of relevant LUT contents, while leaving the rest of the architecture intact. We investigate the dynamic system throughput as a function of the dynamic reconfiguration rate.

关键词： FPGA dynamic partial reconfiguration distributed arithmetic FIR filters hardware

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On LUT cascade realizations of FIR filters

On LUT cascade realizations of FIR filters

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8th Euromicro Conference on Digital System Design

作者： Sasao, T Iguchi, Y Suzuki, T Kyushu Inst Technol Dept Comp Sci & Elect Iizuka Fukuoka 8208502 Japan

ISBN: (纸本)0769524338

This paper first defines the n-input q-output WS function, as a mathematical model of the combinational part of the distributed arithmetic of a finite impulse response (FIR) filter Then, it shows a method to realize the WS function by an LUT cascade with k-input q-output cells. Furthermore, it 1) shows that LUT cascade realizations require much smaller memory than the single ROM realizations;2) presents new design method for a WS function by arithmetic decomposition, and 3) shows design results of FIR filters using FPGAs with embedded memories.

关键词： digital filter distributed arithmetic LUT cascade functional decomposition binary decision diagram FPGA

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A Comparative Study between FPGA and DSP for the Efficient Implementation of FIR Filters 12

A Comparative Study between FPGA and DSP for the Efficient I...

引用

12th International Symposium on Computing and Networking Workshops

作者： Ye, Haolin Wu, Celimuge Yoshinaga, Tsutomu Univ Electrocommun Grad Sch Informat & Engn Chofu Tokyo Japan

ISBN: (纸本)9798331505356;9798331505349

In recent years, field-programmable gate arrays (FPGAs) have achieved a higher performance, higher number of gates, and lower power consumption. Therefore, potential applications of FPGAs have increased, including digital signal processing, which is traditionally performed using digital signal processors (DSPs). This study aims to reveal the advantages of using FPGAs for real-time digital signal processing systems over conventional DSPs. We implemented finite impulse response (FIR) filters with three different lengths to represent applications requiring different levels of filtering precision. These filters were implemented on a low-power Intel Cyclone 10 LP FPGA, large-scale Intel Stratix V GX FPGA, and Texas Instruments TMS320C6747 DSP. To further enrich the comparison, the filters were implemented on an AMD Zen 3 processor. For each platform listed above, we compared the output latency and power consumption data. The results showed that, in the best case, the implementation on FPGA achieved 1/500 the output latency and 1/2 the power consumption of that on DSP.

关键词： FPGA DSP digital signal processing FIR filter distributed arithmetic latency power consumption

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An efficient method for hardware based DCT/IDCT implementation

An efficient method for hardware based DCT/IDCT implementati...

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Conference on Neural Network and distributed Processing

作者： Sun, XT Wu, CK Xidian Univ ISN Natl Key Lab Xian 710071 Peoples R China

ISBN: (纸本)0819442836

Discrete Cosine Transformation (DCT) and Inverse Discrete Cosine Transformation (IDCT) are important parts of many image and video compression system. Unfortunately these operations are extremely computation-intensive in a coding system, it consumes a large amount of resources for computation, especially in a real-time video coding system. In this article an efficient method for hardware based DCT/IDCT implementation is proposed. We combine the vector processing with parallel processing using distributed arithmetic. At the same time the processing elements are pipelined to increase the processing speed and reduce the computation latency, which can also reduce the resource requirement and thus enhance the efficiency.

关键词： DCT IDCT distributed arithmetic row-column decomposition parallel processing

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