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11th Annual IEEE India Conference (INDICON)

作者： Singh, Harpreet Singh, Gurinder Singh, Tarandip Sri Guru Granth Sahib World Univ Dept Elect Engn Fatehgarh Sahib 140406 India

ISBN: (纸本)9781479953646

In this paper, the performance is analyzed based on operating speed, area and memory requirement for the least mean square (LMS) adaptive finite impulse response (FIR) filter using distributed arithmetic (DA). DA technique performs the convolution operation by replacing multipliers with look up tables that result in low resource utilization and high throughput. The throughput and resource utilization factors are related with the number of taps in the DA base unit and these DA base units are required to reduce the memory size and to provide fast updating of memory contents. In this paper, we also analyzed the effect of the number of taps in DA base unit on the memory usage and operating speed of the adaptive FIR filter design.

关键词： distributed arithmetic Least Mean Square Field Programmable Gate Array Digital Signal Processing.

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Design and Verification of low power DA-Adaptive digital FIR filter 7

Design and Verification of low power DA-Adaptive digital FIR...

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7th International Conference on Communication, Computing and Virtualization (ICCCV)

作者： Mankar, Pranav J. Pund, Ajinkya M. Ambhore, Kunal P. Anjankar, Shubham C. GHRCE Dept Elect Nagpur 440016 Maharashtra India MIT Coll Engn Dept Elect & Telecomm Pune 411038 Maharashtra India Ramdeobaba Coll Engn & Management Dept Elect Nagpur 440013 Maharashtra India

A unique pipelined architecture for low-area, low-power, and high-throughput implementation of adaptive filter based on distributed arithmetic (DA) is presented in this paper. distributed arithmetic (DA) is performed to design bit-level architectures for vector-vector multiplication with a direct application for the implementation of convolution, which is necessary for digital filters. Bit-serial operations and look-up tables (LUTs) are used to implement high throughput filters in which only one cycle per bit of resolution regardless of filter length is used. Also parallel lookup table (LUT) updation. Filtering and weight-update operations are concurrently performed to increase the throughput rate of adaptive FIR filter. The new approach of conditional signed carry-save accumulation is used in place of conventional adder based shift accumulation so that reduction of the sampling period and area complexity is easy. However adaptive DA filters also requires recalculating the LUTs for each adaptation which can nullify any performance advantages of DA filtering. The System is designed in Xilinx ISE 9.1 using Verilog HDL and it is routed using Model Sim 6.3. The Verification of the system's behaviour is done using MATLAB 13. DA adaptive filters are advantageous over digital signal processing microprocessor in terms of total area and power consumption. (C) 2016 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://***/licenses/by-nc-nd/4.0/). Peer-review under responsibility of the Organizing Committee of ICCCV 2016

关键词： Adaptive filter distributed arithmetic lookup table (LUT) Xilinx ISE 9.1 MATLAB 13 Model Sim 6.3

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Design and simulation of parallel distributed IIR filter based on FPGA

Design and simulation of parallel distributed IIR filter bas...

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International Conference on Multimedia, Communication and Computing Application（MCCA 2014）

作者： D.X.Sun X.F.Li School of Mechatronical Engineering Beijing Institute of Technology

This paper presents a method of using FPGA to realize IIR digital *** method used full parallel distributed algorithm to reduce the hardware circuit scale on the premise of guaranteeing real time and to solve the problem of floating point calculation in FPGA using fixed-point binary *** a second-order IIR digital filter as an example,this paper used hierarchical method to design the digital filter and its function modules and to verify the hardware circuit through *** results showed that the design of IIR digital filter method has good real-time performance and the hardware circuit size is *** calculation of fixed-point binary number can control the filtering precision effectively,and the lookup table structure changed conveniently,which shows the flexibility of the design.

关键词： Digital filter FPGA distributed arithmetic Fixed-point binary number Simulation

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Design of high-speed FIR filter with distributed Parallel Structure

Design of high-speed FIR filter with Distributed Parallel St...

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2016 IEEE Information Technology,Networking,Electronic and Automation Control Conference(ITNEC 2016)

作者： Mengxue Lei Zhongsong Ma School of Chinese Academy of Sciences University

ISBN: (纸本)9781467391955

To improve the speed of filtering in 320 Mbps digital high-speed demodulation system, a design method of FIR filter with parallel distributed structure is presented. This method consists of two steps, namely FIR filter construction and filter coefficient optimization. In filter construction, the distributed arithmetic is applied to compute the parallel 8channel structure of FIR filter. In addition, this structure i implemented as a target device of Spartan3 in Xilinx ISE 14.7For further optimize the filter's coefficient, fixed-poin representation is put forward. To evaluate the performance o our proposed method, a validation experiment is conducted. The experimental result demonstrates that our method increases the filer speed by 80%, compared with the serial structure.

关键词： high-speed demodulation parallel structure FIR filter distributed arithmetic

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A new k-winners-take-all neural network and its array architecture

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IEEE TRANSACTIONS ON NEURAL NETWORKS 1998年第5期9卷 901-912页

作者： Yen, JC Guo, JI Chen, HC Natl Lien Ho Coll Technol & Commerce Dept Elect Engn Miaoli Taiwan

In this paper, a new neural-network model called WINSTRON and its novel array architecture are proposed. Based on a competitive learning algorithm that is originated from the coarse-fine competition, WINSTRON can identify the fi larger elements or the k smaller ones in a data set. We will then prove that WINSTRON converges to the correct state in any situation, In addition, the convergence rates of WINSTRON for three special data distributions will be derived. In order to realize WINSTRON, its array architecture with low hardware complexity and high computing speed is also detailed. Finally, simulation results are included to demonstrate its effectiveness and its advantages over three existing networks.

关键词： artificial neural network k-winners-take-all competitive learning distributed arithmetic memory-based architecture systolic array

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Hardwarová akcelerace filtrace obrazu

Hardwarová akcelerace filtrace obrazu

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作者： Zelinka, Martin Brno University of Technology

Tato bakalářská práce se zabývá hardwarovou akcelerací filtrace obrazu s využitím FIR filtrů. Definuje základní pojmy týkající se digitálního obraz... 详细信息

Tato bakalářská práce se zabývá hardwarovou akcelerací filtrace obrazu s využitím FIR filtrů. Definuje základní pojmy týkající se digitálního obrazu, popisuje princip filtrace a stručně vysvětluje techniky používané při detekci hran v obraze a při vyhlazování obrazu. Hlavním cílem práce je rozbor několika metod akcelerace FIR filtrů, které jsou vhodné pro realizaci v hardwaru, a následná implementace vybrané metody s možností změny konfigurace za běhu s ohledem na maximální propustnost. V závěru práce je uvedeno vyhodnocení metody z hlediska propustnosti a provedeno srovnání s optimální softwarovou implementací.

关键词： 2D FIR filtr filtrace obrazu hardwarová akcelerace distribuovaná aritmetika RAG algoritmus FPGA 2D FIR filter image filtration hardware-based acceleration distributed arithmetic RAG algorithm FPGA Text

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Implementation of block-based diagonal and quadrantal symmetry type 2D-FIR filter architectures using DA technique

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COMPUTERS & ELECTRICAL ENGINEERING 2024年第PartA期118卷

作者： Reddy, V. Srilatha Juliet, A. Vimala Thuraka, Esther Rani Odugu, Venkata Krishna CVR Coll Engn EIE Dept Hyderabad India SRMIST Chennai India SRM Inst Sci & Technol EIE Dept Chennai India CVR Coll Engn ECE Dept Mangalpalle Telangana India

The efficient architectures of Two-Dimensional (2D) Finite Impulse Response (FIR) filters are proposed for image processing applications. The performance metrics such as power consumption, area, and delay of the architectures can be optimized using VLSI design. The 2D FIR filter architectures can be implemented using parallel or block processing to increase the filter throughput and to prune the number of clock cycles required for image processing. The symmetry in the filter coefficients decreases the number of multipliers, whereas the multiplier block is very complex and a power-consuming block in the filter architecture. In this work, two types of symmetric architectures such as diagonal symmetry and quadrantal symmetry filters are proposed. The remaining multipliers required for the filter architecture are replaced by distributed arithmetic (DA) logic. The memory-based DA reduces the LUT size and hence the area, power, and delay are reduced in the filter architecture. Block processing, symmetry, and DA concepts are introduced here to optimize the 2D FIR filter architecture. The proposed architectures are implemented in 45 nm CMOS technology using Cadence Genus Synthesis tools and area, delay, power, Area-Delay Product (ADP), and Power-Delay Product (PDP) results are obtained and compared with state-of-the-art works. The ADP value of the proposed diagonal symmetry architecture is decreased by a maximum of 73.34 %, and a minimum of 20.39 %, and the PDP value is decreased by a maximum of 90.28 %, and a minimum of 21.27 % when compared to the existing works. The ADP and PDP values of the proposed quadrantal symmetry are decreased by a minimum of 23.62 %, and 27.74 % when compared to existing works, respectively.

关键词： Two-dimensional FIR filter distributed arithmetic Symmetry in coefficients Block processing Lut-based multipliers ADP PDP

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Architectural implementation of modified K-best algorithm for detection in MIMO systems

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MICROPROCESSORS AND MICROSYSTEMS 2020年 74卷 103010-103010页

作者： Edward, A. Shirly Malarvizhi, S. SRM Inst Sci & Technol Dept ECE Chennai Tamil Nadu India

We present novel architectures for the modified K-best algorithm and its very-large-scale integration implementation for spatially multiplexed wireless multiple-input multiple-output systems. The objective was to propose a simplified architecture based on the algorithm and to significantly improve the suitability for hardware implementation. Two different architecture designs were proposed: a distributed arithmetic-based tree-search detector and a breadth-first search sphere detector. The implementations were performed to obtain a configurable architectural solution for different antenna configurations and constellations. The synthesis analysis shows that the proposed architectures achieve a throughput of > 500 Mbps with reduced hardware complexity compared to previously reported architectures. (C) 2020 Elsevier B.V. All rights reserved.

关键词： MIMO distributed arithmetic FPGA Latency Throughput

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A high-speed multiplier-free realization of IIR filter using ROM's and elevated signal rate

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2001年第6期E84A卷 1479-1487页

作者： Sakunkonchak, T Tantaratana, S Thammasat Univ Sirindhorn Int Inst Technol Elect Engn Program Pathumthani 12121 Thailand

In this paper, we propose a high-speed multiplier-free realization using ROM's to store the results of coefficient scalings in combination with higher signal rate and pipelined operations, without the need of hardware multipliers. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or throughput). Examples are given comparing the proposed realization with the distributed arithmetic (DA) realization and direct-form realization with power-of-two coefficients. Results show that with proper choices of the parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization, while it is much faster than the direct-form with slightly more hardware.

关键词： multiplier-free realization distributed arithmetic powers-of-two coefficients ROM's carry-lookahead adders

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Low power low area VLSI implementation of adaptive FIR filter using DA for decision feed back equalizer

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MICROPROCESSORS AND MICROSYSTEMS 2022年 93卷

作者： Vijetha, K. Naik, Rajendra B. Osmania Univ Univ Coll Engn Hyderabad Telangana India

In this paper, a low-complexity pipelined adaptive FIR filter is designed using distributed arithmetic (DA) architecture for signal processing applications. Generally adaptive filters will occupy more area and power consumption because of using memories in the filters for partial product (PP) generation. To get rid of this, We use the pipeline concept to reduce the registers in the filters and also to reduce the area further compressor adders are used in the adaptive filter architectures instead of using normal adders. With these two concepts the area and power consumption of the adaptive filters will be reduced. The proposed design is coded in Verilog HDL language and synthesized in Synapsis design compiler tool with SAED 90 nm technology for finding the area, power, minimum sampling period, maximum sampling frequency, area delay product (ADP), power delay product (PDP). By using proposed adaptive filter we can design and implement higher order filters more easily and also the complexity of the proposed design is very less when compared with the existing designs. When we observe the synthesis results the proposed design will occupy 30% less area when compared with the two memories based existing architecture. Also the power consumption is 25% less when compared with the block based adaptive fillers. The ADP and PDP of the proposed design is very less when compared with existing architectures. The proposed design is well suited for signal processing application designs such as adaptive decision feed back equalizers for removing the signal noises and inter symbol interference, hearing aids, ECG signal analysis and software defined radio.

关键词： Pipelined LMS adaptive FIR filter distributed arithmetic Compressor adder

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