In this study, the performance of a multiprocessor for a state-space digital filter using block-state realization is analyzed by VLSI evaluation. The multiprocessor realization proposed by the authors is a two-dimensi...
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In this study, the performance of a multiprocessor for a state-space digital filter using block-state realization is analyzed by VLSI evaluation. The multiprocessor realization proposed by the authors is a two-dimensional SIMD structure using the same processors. The method can realize a digital filter with high throughput and accuracy, while suppressing the increase of PE and the duration. As a first step, the VLSI evaluation of the processor from the viewpoint of the distributed arithmetic is attempted. It is shown that sixteen 17th-order inner-product operations can be executed with a very high execution speed of 3.92 MHz (0.6 mu m CMOS standard cell). It is then shown that a 16th-order filter can be realized by the microprocessor based on the proposed method, with a high sampling frequency above 250 MHz, which has previously been impossible. The performance obtained by the block-state realization digital filter is considered after reduction to multirate signal processing, and the sampling frequency is determined based on the indicated property. It is a processing performance that cannot be obtained by generally improving the speed of the hardware. It is further shown by the VLSI evaluation that the operation speed of the processor remains almost constant even if the order is raised, demonstrating the effectiveness of the proposed method. (C) 1999 Scripta Technica.
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