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检索条件"主题词=distributed arithmetic"

共 221 条记录，以下是81-90 订阅

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Inner Products Computation Using Folded Waveforms and distributed arithmetic Principles

Inner Products Computation Using Folded Waveforms and Distri...

引用

54th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Pham, Duc-Minh Premkumar, A. B. Madhukumar, A. S. Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

ISBN: (纸本)9781612848570

In this paper, inner products using a new number system called the Folding Residue Number System (FRNS) and distributed arithmetic (DA) principles is proposed. The advantage of this new number system is that it allows digital filters to be implemented directly from the analog signal by decomposing and folding it in several parallel channels. Folding Residues extracted together with the folding information obtained from the folding circuits are processed using DA principles in implementing the filtering algorithm. The FRNS has the same complexity of computation as that of the Residue Number System (RNS) but intermediate steps such as conversion of the analog signal into its binary equivalents and subsequently into residues required in RNS are eliminated. Moreover, smaller word length of the folding residues coupled with DA results in faster implementation of the filtering algorithms.

关键词： Clocks DA principles FRNS Finite impulse response filter Table lookup analog signal binary equivalents distributed arithmetic distributed arithmetic principles filtering algorithm filtering theory folded waveforms folding residue number system inner products computation residue number systems waveform analysis

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VLSI implementation of distributed arithmetic based block adaptive finite impulse response filter

VLSI implementation of distributed arithmetic based block ad...

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International Conference on NanoTechnology - Ideas, Innovation and Industries

作者： Chowdari, Pratyusha Ch Seventline, J. B. GRIET Hyderabad 500090 India GITAM Univ Visakhapatnam 530045 Andhra Pradesh India

In this paper, an efficient VLSI architecture of distributed arithmetic (DA) based block least mean square (BLMS) adaptive finite impulse response (ADFIR) filter implementation with parallel processing is proposed. In DA scheme, the filter partial products are precomputed and saved in lookup table (LUT) and then by using shift and accumulation operations filtering can be done. To improve the efficiency, a high level of parallelism is incorporated in the design of variable coefficient ADFIR filter. The parallel LUT followed by shift-accumulate operations replaces multiply and accumulate (MAC) operations. By using BLMS algorithm in ADFIR filter with block length P gives P times fast throughput. Since memory reuse concept is used, the design requires less number of registers to calculate output vector and coefficient increment vector. The proposed design is implemented on FPGA. The implementation results indicate that the proposed design is a low power and high speed architecture. The proposed structure provides 47.4% less power and 22.7% less delay when compared to existing designs. (C) 2019 Elsevier Ltd. All rights reserved.

关键词： distributed arithmetic Block least mean square Algorithm Block processing Adaptive finite impulse response filter Multiply and accumulate

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An Efficient DFT Implementation using Modified Group distributed arithmetic 6

An Efficient DFT Implementation using Modified Group Distrib...

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6th International Conference on Signal Processing and Integrated Networks (SPIN)

作者： Kumar, Santhosh S. R. Veeramachaneni, Sreehari Mahammad, Noor Sk Indian Inst Informat Technol Design & Mfg Kanchee Dept ECE Chennai Tamil Nadu India Gokaraju Rangaraju Inst Engn & Technol Dept ECE Hyderabad Telangana India Indian Inst Informat Technol Design & Mfg Kanchee Dept CSE Chennai Tamil Nadu India

ISBN: (纸本)9781728113807

Many of the modern signal/ image processing applications use Discrete Fourier Transform (DFT) as one of the core functional elements to process the input signal/image from one domain to another. Hardware design of the DFT is complex and many researchers have proposed variety of methods to implement it. Computational complexity of ID, N-point DFT is O(N-2). distributed arithmetic is one of the promising and efficient technique to implement any discrete orthogonal transform. This paper proposes an efficient approach to implement DFT using distributed arithmetic. The proposed technique exploits the repetitive pattern of coefficients and stores efficiently in the memory and reduces the storage by 75% compared to the existing group distributed arithmetic for 8-point DFT. The proposed approach uses the property of group distributed arithmetic efficiently in the architecture.

关键词： Discrete Fourier Transform distributed arithmetic Discrete Orthogonal Transform Signal Processing Image Processing

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Area-efficient FIR filter design on FPGAs using distributed arithmetic

Area-efficient FIR filter design on FPGAs using distributed ...

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6th IEEE International Symposium on Signal Processing and Information Technology

作者： Longa, Patrick Miri, Ali Univ Ottawa Sch Informat Technol & Engn Ottawa ON K1N 6N5 Canada

ISBN: (纸本)9780780397538

In this paper, a highly area-efficient multiplier-less FIR filter is presented. distributed arithmetic (DA) has been used to implement a bit-serial scheme of a general asymmetric version of an FIR filter, taking optimal advantage of the 4-input LUT-based structure of FPGAs. Furthermore, we have introduced a modification in the accumulator stage to achieve further savings. The proposed filter has been designed and synthesized with Altera Quartus H, and inplemented on a Stratix FPGA device Our results show reduced area requirements in comparison to previous LUT-less DA architectures.

关键词： FIR filter FPGA DSP distributed arithmetic lookup table (LUT)

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An Efficient Modified distributed arithmetic Architecture Suitable for FIR Filter 6

An Efficient Modified Distributed Arithmetic Architecture Su...

引用

6th International Conference on Wireless Communications, Signal Processing and Networking (IEEE WiSPNET)

作者： Narendiran, S. Jayakumar, E. P. Natl Inst Technol Dept Elect & Commun Engn Calicut Kerala India

ISBN: (纸本)9781665440868

One of the essential components of a Digital Signal Processing (DSP) system is the Finite Impulse Response (FIR) filter. FIR filter uses the Multiply and Accumulate (MAC) operation for its computation. Conventional MAC units are slow and consume high power, making them unsuitable for energy-constrained devices. The MAC operations in FIR filter uses constant filter coefficients as one of its inputs. This situation is well suited for a bit-serial technique such as distributed arithmetic (DA). However, the traditional DA has the drawback of using huge memory resources as the filter order increases. An efficient LUT-less Modified distributed arithmetic architecture is proposed in this paper to solve the memory problem. This architecture removes the need for precomputation of weighted sums needed for the LUT in a DA using multiplexers and adders. Also, the architecture is designed to extend the range of input values. Further, a 16-Tap FIR filter is designed, synthesized with Xilinx ISE, and implemented for an XC4VSX35-FF668-10 based FPGA to measure the performance of this architecture. Our implementation results show that the design uses fewer resources and achieves faster filtering than the filter's previous implementations.

关键词： distributed arithmetic Multiply and Accumulate FIR Filter FPGA

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Reconfigurable FIR Filter Using distributed arithmetic on FPGAs

Reconfigurable FIR Filter Using Distributed Arithmetic on FP...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Kumm, Martin Moeller, Konrad Zipf, Peter Univ Kassel Digital Technol Grp Kassel Germany

ISBN: (纸本)9781467357623;9781467357609

An architecture for a dynamically run-time reconfigurable finite impulse response (FIR) filter is presented in this work. It is based on distributed arithmetic (DA) combined with a look- up table (LUT) reduction technique which allows the direct mapping to reconfigurable LUTs (CFGLUT) of the latest Xilinx FPGAs. The resulting FIR filter can be reconfigured with arbitrary coefficients which are only limited by their length and word size. The number of filter instances for reconfiguration is only limited by the block memory of the FPGA which typically allows hundreds of different configurations. The proposed reconfigurable architecture consumes 16% less slices on average than a fixed coefficient DA filter generated by Xilinx Coregen. As the direct mapping to CFGLUTs leads to invalid filter output during reconfiguration, an alternative architecture is proposed which avoids this limitation at the cost of 19% more slice resources on average. Using a parallel reconfiguration scheme, reconfiguration times of about 100 ns could be achieved.

关键词： FIR filters distributed arithmetic field programmable gate arrays

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distributed arithmetic FIR Filter for Electrical Resistance Tomography System

Distributed Arithmetic FIR Filter for Electrical Resistance ...

引用

2011 China Control and Decision Conference(2011中国控制与决策会议 CCDC)

作者： Cong Xu Feng Dong Zhiqiang Zhang Tianjin Key Laboratory of Process Measurement and Control School of Electrical Engineering and Automation Tianjin University Tianjin CO 300072 P.R. China

The digital FIR filter is widely used in electronic instruments. It is the time delay of the filter that affects the real-time performance of the conventional ERT system. This paper discusses the advantages of applying the distributed digital FIR filter in ERT system. Compared with the traditional filter, both the SNR and the channel consistence were improved to some extent. More importantly, the real-time performance has been improved;especially the data acquisition rate is increased from 600 frames per second to 1040 frames per second for the sixteen electrode system.

关键词： Digital filter FIR distributed arithmetic ERT

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distributed arithmetic Architectures for FIR Filters-A Comparative review 2

Distributed Arithmetic Architectures for FIR Filters-A Compa...

引用

2nd IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET)

作者： NagaJyothi, Grande SriDevi, Sriadibhatla VIT Univ Sch Elect Engn Vellore Tamil Nadu India

ISBN: (纸本)9781509044429

Finite impulse response (FIR) filter is an influential block in various signal processing applications. The complexities in VLSI implementation of FIR filters is dominated by the number of multiply and accumulate (MAC) operations. distributed arithmetic (DA) is an alternative technique where the MAC operations can be replaced by a series of look-up tables and addition operations. FIR filter based on DA are computationally efficient because of high degree of mechanization involved in the implementation of MAC operations using DA. Many reconfigurable and non-reconfigurable FIR filter architectures can be developed using DA. This paper reviews the existing FIR filter architectures based on DA. LUT based DA and LUT-less DA are the significant methods in the implementation of non-reconfigurable filters. This brief summarizes the area and power reports of the existing non-reconfigurable FIR filter architectures based on both LUT based DA and LUT-less DA. One dimensional and two dimensional systolic DA based architectures for FIR filter implementation are also briefed. DA based adaptive FIR techniques are explained. This paper presents the comparative results of FIR and adaptive FIR filter architectures in terms of area, power, area-delay product, minimum cycle period and energy per sample. This survey can form a basis for further research on DA based FIR filter architectures.

关键词： distributed arithmetic LUT FIR Filter OBC Reconfigurable FIR filter adaptive

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Domain-specific reconfigurable array for distributed arithmetic

Domain-specific reconfigurable array for distributed arithme...

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13th International Conference on Field-Programmable Logic and Applications (FPL 2003)

作者： Khawam, S Arslan, T Westall, F Univ Edinburgh Sch Elect & Engn Edinburgh EH9 3JL Midlothian Scotland Inst Syst Level Integrat Livingston EH54 7EG Scotland EPSOM Scotland Design Ctr Livingston EH54 7EG Scotland

ISBN: (纸本)3540408223

distributed arithmetic techniques are widely used to implement Sum-of-Products computations such as calculations found in multimedia applications like FIR filtering and Discrete Cosine Transform. This paper presents a flexible, low-power and high throughput array for implementing distributed arithmetic computations. Flexibility is achieved by using an array of elements arranged in an interconnect mesh similar to those employed in conventional FPGA architectures. We provide results which demonstrate a significant reduction in power consumption in addition to improvements in timing and area over standard FPGA architectures.

关键词： embedded reconfigurable array programmable distributed arithmetic FPGA domain specific low-power

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Efficient wavelet transform on FPGA using advanced distributed arithmetic

Efficient wavelet transform on FPGA using advanced distribut...

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8th International Conference on Electronic Measurement and Instruments

作者： Chen Jing Hou Yuan Bin Xian Univ Sci & Technol Xian 710000 Peoples R China

Recently, wavelet transformation has shown itself as a useful tool in many fields. Due to the increasing important of this technique, there was a growing need to embed it into a real system. However, the computation-intensive nature obstructs its way for a lot of applications needing real-time control. By using high-density field programmable logic devices (FPGAs), the discrete wavelet transformation obtains higher processing speed and lower costs than other implementation methods. The polyphase filterbank structure and the improved distributed architecture are adopted in this paper, to speedup wavelet computation. Performance results show that the distributed arithmetic formulation results in a considerable performance gain.

关键词： FPGA wavelet distributed arithmetic virtex

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