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Scheduling with bus access optimization for distributed embedded systems

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systems 2000年第5期8卷 472-491页

作者： Eles, P Doboli, A Pop, P Peng, Z Linkoping Univ Dept Comp & Informat Sci S-58183 Linkoping Sweden Univ Cincinnati Dept Elect & Comp Engn & Comp Sci Cincinnati OH 45221 USA

In this paper, we concentrate on aspects related to the synthesis of distributed embedded systems consisting of programmable processors and application-specific hardware components. The approach is based on an abstract graph representation that captures, at process level, both dataflow and the flow of control, Our goal is to derive a worst case delay by which the system completes execution, such that this delay is as small as possible;to generate a logically and temporally deterministic schedule;and to optimize parameters of the communication protocol such that this delay is guaranteed. We have further investigated the impact of particular communication infrastructures and protocols on the overall performance and, specially, how the requirements of such an infrastructure have to be considered for process and communication scheduling. Not only do particularities of the underlying architecture have to be considered during scheduling but also the parameters of the communication protocol should be adapted to fit the particular embedded application, The optimization algorithm, which implies both process scheduling and optimization of the parameters related to the communication protocol, generates an efficient bus access scheme as well as the schedule tables for activation of processes and communications.

关键词： communication synthesis distributed embedded systems process scheduling real-time systems system synthesis time-triggered protocol

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Rapid performance re-engineering of distributed embedded systems via latency analysis and k-level diagonal search

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JOURNAL OF PARALLEL AND distributed COMPUTING 2006年第1期66卷 19-31页

作者： Park, J Ryu, M Hong, S Lo Bello, L Hanyang Univ Coll Informat & Commun Seoul 133791 South Korea Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul 151742 South Korea Univ Catania Dept Comp Engn & Telecommun Catania Italy

This paper presents a systematic methodology aimed at rapid and cost-effective re-engineering of distributed embedded systems. We define embedded system re-engineering as an analysis and alteration of a legacy system, to guarantee newly imposed performance requirements such as throughput and input-to-output latency. Our methodology pinpoints performance bottlenecks of a system and selectively upgrades processing elements at the least cost. Inputs for our methodology include a system design specified by a process network over a set of processing elements and a new throughput requirement. The output is a set of scaling factors that represent the ratios of the performance upgrades for processing elements. Our methodology works in two steps. First, it estimates the latency of each process and identifies bottleneck processes. Second, it derives a system of constraints with scaling factors being free variables and formulates an optimization problem. Then, it solves the optimization problem for scaling factors with an objective of minimizing upgrade cost. For this methodology, we propose an accurate latency analysis technique for precedence-constrained tasks under preemptive fixed priority scheduling. We also propose a k-level diagonal search algorithm that allows us to trade optimality for search time. Our experimental results show the effectiveness of the proposed re-engineering approach. (c) 2005 Elsevier Inc. All rights reserved.

关键词： distributed embedded systems re-engineering latency analysis performance/cost optimization

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A decomposition-based approach to optimization of TTP-based distributed embedded systems

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JOURNAL OF systems ARCHITECTURE 2018年 91卷 53-61页

作者： Zhang, Ming Zheng, Nenggan Li, Hong Gu, Zonghua Zhejiang Univ Coll Comp Sci Hangzhou 310027 Zhejiang Peoples R China Zhejiang Univ Qiushi Inst Adv Studies Hangzhou 310027 Zhejiang Peoples R China

Time-Triggered Protocol (TTP) is an industry-standard bus protocol widely-used in safety-critical avionics distributed embedded systems. Design space exploration for TTP-based distributed embedded system involves searching through a vast design space of all possible task-to-processor mappings and bus access configurations. In this paper, we consider the task model of periodic tasks on multiple processor nodes connected by the TTP bus communicating via asynchronous buffers based on non-blocking read/write semantics, and present two optimization frameworks based on Logic-Based Benders Decomposition (LBBD), by dividing the design problem into a master problem of optimizing task-to-processor mapping to minimize bus bandwidth utilization, and a sub-problem of optimizing the bus access configuration subject to deadline constraints on a set of end-to-end paths, and each problem is solved with a suitable optimization solver. Experimental results demonstrate the feasibility and scalability of the proposed techniques.

关键词： distributed embedded systems Time-Triggered Protocol Optimization

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Designing end-to-end resource reservations in predictable distributed embedded systems

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REAL-TIME systems 2017年第6期53卷 916-956页

作者： Ashjaei, Mohammad Khalilzad, Nima Mubeen, Saad Behnam, Moris Sander, Ingo Almeida, Luis Nolte, Thomas Malardalen Univ Vasteras Sweden Malardalen Univ Sch Innovat Design & Engn Vasteras Sweden KTH Royal Inst Technol Stockholm Sweden Univ Porto Inst Telecomunicaes Oporto Portugal

Contemporary distributed embedded systems in many domains have become highly complex due to ever-increasing demand on advanced computer controlled functionality. The resource reservation techniques can be effective in lowering the software complexity, ensuring predictability and allowing flexibility during the development and execution of these systems. This paper proposes a novel end-to-end resource reservation model for distributed embedded systems. In order to support the development of predictable systems using the proposed model, the paper provides a method to design resource reservations and an end-to-end timing analysis. The reservation design can be subjected to different optimization criteria with respect to runtime footprint, overhead or performance. The paper also presents and evaluates a case study to show the usability of the proposed model, reservation design method and end-to-end timing analysis.

关键词： End-to-end reservation Response time analysis Server design distributed embedded systems Resource reservation

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A time synchronization protocol for large-scale distributed embedded systems with low-precision clocks and neighbor-to-neighbor communications

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JOURNAL OF NETWORK AND COMPUTER APPLICATIONS 2018年第Mar.期105卷 123-142页

作者： Naz, Andre Piranda, Benoit Bourgeois, Julien Goldstein, Seth Copen UBFC FEMTO ST Inst CNRS F-25200 Montbeliard France Carnegie Mellon Univ Pittsburgh PA 15213 USA

In this paper, we propose the Modular Robot Time Protocol (MRTP), a network-wide time synchronization protocol for modular robots (a class of distributed embedded systems) with neighbor-to-neighbor communications and potentially low-precision clocks. Our protocol achieves its performance by combining several mechanisms: central time master election, fast and recursive propagation of synchronization waves along the edges of a breadth-first spanning-tree, low-level timestamping and per-hop compensation for communication delays using the most-appropriate method, and clock skew compensation using linear regression. We evaluate our protocol on the Slinky Blocks system both on hardware and through simulations. Experimental results show that MRTP can potentially manage real systems composed of up to 27, 775 Slinky Blocks. We observe that the synchronization precision depends on the hop distance to the time master, the synchronization periods and the number of synchronization points used for the linear regressions. Furthermore, we show that our protocol is able to keep a Slinky Blocks system synchronized to a few milliseconds, using few network resources at runtime, even-though the Blinky Blocks hardware clocks exhibit very poor accuracy and resolution. We compare MRTP to existing synchronization protocols ported to fit our system model. Simulation results show that MRTP can achieve better synchronization precision than the most precise compared protocols while sending more than half less messages in compact systems.

关键词： Time synchronization distributed embedded systems Modular robotics

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Code generation for distributed embedded systems with VDM-RT

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DESIGN AUTOMATION FOR embedded systems 2019年第3-4期23卷 153-177页

作者： Hasanagic, Miran Fabbri, Tommaso Larsen, Peter Gorm Bandur, Victor Tran-Jorgensen, Peter Ouy, Julien Aarhus Univ Aarhus Denmark Univ Pisa Pisa Italy ClearSy Marseille France

Developing embedded systems that are distributed is a challenging endeavour, since they need to ensure system-wide properties as well as existence of a large number of possible candidate system architectures. Various model based techniques advocate raising the abstraction level in order to support a holistic view of such a distributed embedded system. Furthermore, automatically generating implementation specific code from models can support realisation efforts including avoiding inconsistencies between model and code. In this paper we present how such efforts can be aided for a distributed embedded system modelled in the real time dialect of the Vienna Development Method, VDM-RT, by means of automatic code generation. The contributions in this paper are (1) code generation capabilities for distributed embedded system modelled in VDM-RT;(2) demonstration of its applicability for an industrial case study involving a distributed interlocking system from the railways domain. Additionally, we discuss the balance between code generation for a model, which assumes idealised communication (no messages lost), and manually produced code, e.g. in the industrial case study legacy low-level code ensures fault-tolerant communication in the final implementation.

关键词： distributed embedded systems Code generation Co-simulation Validation VDM-RT

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FLEXIBLE COMMUNICATION STRUCTURE FOR distributed embedded systems

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IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES 1986年第4期133卷 201-211页

作者： SLOMAN, M KRAMER, J MAGEE, J TWIDLE, K Department of Computing Imperial College of Science & Technology London UK

The paper describes an extensible communication system for Conic, an architecture for distributed embedded systems. Conic provides a high level programming language with interprocess communication primitives suited to both local and remote communication. These primitives are sufficiently powerful to be used for applications programming yet simple and efficient enough for programming system software. The communication system which supports these primitives is itself implemented in the Conic language. It provides a very simple datagram-like service, over interconnected local area networks. The configuration flexibility of Conic is exploited to allow extension of the basic communication system to give additional services such as virtual circuit or routing. The paper also relates the Conic communication system to the ISO Reference Model and indicates some of the problems of using the model. An earlier version of this paper was presented at the 5th IFAC Workshop on distributed Computer Control systems, Sabi Sabi, South Africa, May 1983.

关键词： Computer architecture applications programming distributed processing Computer networks and techniques distributed embedded systems high level programming language extensible communication system ISO Reference Model routing high level languages Conic computer architecture system software programming High level languages interprocess communication primitives virtual circuit interconnected local area networks computer networks datagram-like service

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An FSM-based monitoring technique to differentiate between follow-up and original errors in safety-critical distributed embedded systems

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MICROELECTRONICS JOURNAL 2011年第6期42卷 863-873页

作者： Sedaghat, Yasser Miremadi, Seyed Ghassem Sharif Univ Technol Dependable Syst Lab Tehran Iran

Nowadays, distributed embedded systems are employed in many safety-critical applications such as X-by-Wire. These systems are composed of several nodes interconnected by a network. Studies show that a transient fault in the communication controller of a network node can lead to errors in the fault site node (called original errors) and/or in the neighbor nodes (called follow-up errors). The communication controller of a network node can be halted due to an error, which may be a follow-up error. In this situation, a follow-up error leads to halt the correct operation of a fault-free controller while the fault site node, i.e. the faulty controller, still continues its operation. In this paper, an analysis shows that the occurrence probability of follow-up errors in communication protocols is noticeable. Consequently, it is important to provide a technique to recognize the error's nature, i.e. original or follow-up in each node. This paper proposes a novel low-cost monitoring technique to differentiate follow-up errors from original errors. The proposed technique is based on monitoring the operational states of a communication controller. In this paper, this technique has been applied to the FlexRay protocol. However, it is applicable for all communication protocols having an FSM-based description such as FlexRay, TTP/C, and TT-Ethernet. To evaluate the monitoring technique, a FlexRay-based network including 4 nodes was designed and implemented. The low-cost monitoring technique was as well implemented inside each node of the network. A total of 135,600 transient bit-flip faults were injected in the communication controller of one node. The results showed that about 6.0% of injected faults lead to original errors. This figure for follow-up errors was about 6.1%. The results as well showed that the accuracy of the proposed technique to differentiate between the follow-up and original errors is about 97% at merely 1.4% hardware overhead. This level of accuracy and cost m

关键词： distributed embedded systems Error propagation Follow-up errors FlexRay protocol Transient faults FSM-based monitoring

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The Signal Synchronous Multiclock Approach to the Design of distributed embedded systems

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IEEE TRANSACTIONS ON PARALLEL AND distributed systems 2010年第5期21卷 641-657页

作者： Gamatie, Abdoulaye Gautier, Thierry INRIA Lille Nord Europe LIFL CNRS UMR 8022 F-59650 Villeneuve Dascq France INRIA Rennes Bretagne Atlantique F-35042 Rennes France

This paper presents the design of distributed embedded systems using the synchronous multiclock model of the SIGNAL language. It proposes a methodology that ensures a correct-by-construction functional implementation of these systems from high-level models. It shows the capability of the synchronous approach to apply formal techniques and tools that guarantee the reliability of the designed systems. Such a capability is necessary and highly worthy when dealing with safety-critical systems. The proposed methodology is demonstrated through a case study consisting of a simple avionic application, which aims to pragmatically help the reader to understand the manipulated formal concepts, and to apply them easily in order to solve system correctness issues encountered in practice. The application functionality is first modeled as well as its distribution on a generic hardware architecture. This relies on the endochrony and endo-isochrony properties of SIGNAL specifications, defined previously. The considered architectures include asynchronous communication mechanisms, which are also modeled in SIGNAL and proved to achieve message exchanges correctly. Furthermore, the synchronizability of the different parts in the resulting system is addressed after its deployment on a specific execution platform with multirate clocks. After all these steps, a distributed code can be automatically generated.

关键词： distributed embedded systems correct-by-construction design methodology safety-critical domains formal validation synchronous model asynchronous mechanisms multiclock SIGNAL language

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Exploration of communication models in the design of distributed embedded systems

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IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING 2007年第3期2卷 402-404页

作者： Kobayashi, Kazutaka Shiraishi, Takashi Zakaria, Nurul Azma Yamasaki, Ryosuke Yoshida, Norihiko Narazaki, Shuji Saitama Univ Grad Sch Sci & Engn Saitama 3388570 Japan Nagasaki Univ Fac Engn Nagasaki 8528521 Japan

distributed embedded systems involve communication in various layers, and therefore their design is more difficult than of single embedded systems. This paper presents how communication exploration can be done in a design process of distributed embedded systems using an example of event-triggered and time-triggered communication. A design process begins from abstract specification without assuming any communication category, then explores the categories in a stepwise manner, followed by physical implementation synthesis. This encourages stepwise decision making, component and framework reuse, and early stage verification. (c) 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

关键词： distributed embedded systems network communication model-driven architecture stepwise refinement design

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