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16th ACM SIGPLAN International Workshop on Erlang (Erlang)

作者： Azuma, Kagumi Ishiura, Nagisa Yoshida, Nobuaki Kanbara, Hiroyuki Kwansei Gakuin Univ Dept Informat 2-1 Gakuen Sanda Hyogo Japan ASTEM RI KYOTO Kyoto Japan

ISBN: (纸本)9781450351799

This paper presents a distributed memory architecture for dedicated hardware automatically synthesized from Erlang programs. Our team had developed a framework for generating embedded systems controllers whose behavior was specified by a subset of Erlang, where each process was mapped into hardware (a logic circuit) running independently of the circuits for the other processes. However, the resulting hardware was not of practical use because it shared a single main memory potentially accessed by all the circuits for the processes simultaneously. To address this issue, in this paper, the main memory is partitioned into banks so that each process can access its own memory independently of the other processes. In order to keep the interconnections for message passing to a practical size, a bus architecture is employed where send requests are arbitrated by an arbiter (logic circuit). In order to make the resulting hardware as small as possible, a garbage collection circuit is shared among the circuits for the processes also under the control of the arbiter. From a simple Erlang speci. cation, Verilog HDL codes for necessary hardware to construct a system has been generated.

关键词： Erlang high-level synthesis distributed memory architecture embedded systems ACAP

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Energy-efficient sorting with the distributed memory architecture ePUMA 14

Energy-efficient sorting with the distributed memory archite...

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13th IEEE International Symposium on Parallel and distributed Processing with Applications

作者： Karlsson, Andreas Sohl, Joar Liu, Dake Linkoping Univ Dept Elect Engn S-58183 Linkoping Sweden

ISBN: (纸本)9781467379526

This paper presents the novel heterogeneous DSP architecture ePUMA and demonstrates its features through an implementation of sorting of larger data sets. We derive a sorting algorithm with fixed-size merging tasks suitable for distributed memory architectures, which allows very simple scheduling and predictable data-independent sorting time. The implementation on ePUMA utilizes the architecture's specialized compute cores and control cores, and local memory parallelism, to separate and overlap sorting with data access and control for close to stall-free sorting. Penalty-free unaligned and out-of-order local memory access is used in combination with proposed application-specific sorting instructions to derive highly efficient local sorting and merging kernels used by the system-level algorithm. Our evaluation shows that the proposed implementation can rival the sorting performance of high-performance commercial CPUs and GPUs, with two orders of magnitude higher energy efficiency, which would allow high-performance sorting on low-power devices.

关键词： DSP ePUMA sorting sorting programs grade Digital signal processing Desmoplakin Gene distributed memory architecture Local memory energy component Energy efficiency Sorting algorithm architecture Access to Information information retrieval

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Developing the Parallelization Methods for Finding the All-Pairs Shortest Paths in distributed memory architecture 38

Developing the Parallelization Methods for Finding the All-P...

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IEEE 38th International Performance Computing and Communications Conference (IPCCC)

作者： Alghamdi, Mohammed He, Ligang Zhou, Yujue Li, Junyu Univ Warwick Dept Comp Sci Coventry W Midlands England King Khalid Univ Dept Informat Syst Abha Saudi Arabia

ISBN: (纸本)9781728110257

The All-Pairs Shortest Paths (APSP) is a fundamental graph problem aiming to find the shortest path between any two nodes in a graph. In this paper, a new method is presented to solve the APSP problem for big graphs on distributed systems. In this method, a graph is partitioned judiciously and then processed in parallel. In particular, the graph is first pre-processed to prepare the partition in the computation stages. After the graph is partitioned into smaller sub-graphs, a traditional shortest path algorithm, such as the Floyd-Warshall algorithm or the Dijkstra's algorithm, can be used to find the APSP in each sub-graph. Finally, through the common nodes between the sub-graphs, the local results in each sub-graph are combined to establish the APSP for the entire graph. Our method is implemented with MPI. Two different communication patterns among partitions (and processes) are proposed to achieve the parallelization and the combination of the local results. We then conducted extensive experiments on a high performance cluster. The experimental results show that comparing with the existing solution, our method is able to accelerate the solving of the APSP problem significantly.

关键词： All-Pairs Shortest Path Graph partition parallel processing distributed memory architecture

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Parallelization of Algorithms for Image Stitching Using distributed memory architecture

Parallelization of Algorithms for Image Stitching Using Dist...

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International Conference on Nascent Technologies in Engineering (ICNTE)

作者： Satoskar, Ananya Nambiar, Vishnu Mohan, Aishwarya Rainy, Christina Gadhikar, Lakshmi Fr Conceicao Rodrigues Inst Technol Dept Informat Technol Vashi Navi Mumbai India

ISBN: (纸本)9781509027941

The efficient use of satellite images for practical purposes depends upon the ability to combine them for the purposes of analysis. However, this process involves many computationally intensive computer vision algorithms. Assembling large images usually requires costly hardware with a large amount of memory. This paper addresses this problem by proposing a system that implements algorithms required in the process of image stitching, viz. algorithms for feature detection, feature description, feature matching, image transformation and image compositing, in parallel on a distributed memory architecture. The proposed system aims to improve the performance of the image stitching process while providing a more easily scalable system.

关键词： image stitching distributed memory architecture parallel computing

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Energy-efficient and High Throughput Sparse distributed memory architecture

Energy-efficient and High Throughput Sparse Distributed Memo...

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IEEE International Symposium on Circuits and Systems

作者： Mingu Kang Eric P. Kim Min-sun Keel Naresh R. Shanbhag Dept. Electrical and Computer Engineering University of Illinois at Urbana-Champaign

ISBN: (纸本)9781479983926

This paper presents an energy-efficient VLSI implementation of Sparse distributed memory (SDM). High throughput and energy-efficient Hamming distance-based address decoder (CM-DEC) is proposed by employing compute memory [1], where computation is deeply embedded into a memory (SRAM). Hierarchical binary decision (HBD) is also proposed to enhance area- and energy-efficiency of read operation by minimizing data transfer. The SDM is employed as an auto-associative memory with four read iterations and 16×16 binary noisy input image with input error rates of 15%, 25 %, and 30%. The proposed SDM achieves 39× smaller energy delay product with 14.5× and 2.7× reduced delay and energy, respectively as compared to conventional digital implementation of SDM in 45 nm SOI CMOS process with output error rate degradation less than 0.4%.

关键词： Energy efficiency memory architecture distributed memory architecture read operation Throughput

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Orthogonal reduction of dense matrices to bidiagonal form on computers with distributed memory architectures

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PARALLEL COMPUTING 1998年第2期24卷 305-313页

作者： Kuznetsov, SV Russian Acad Sci Inst Math Novosibirsk 630090 Russia

In this paper, we describe a parallel implementation for the blocked reduction of dense matrices to bidiagonal form by Householder transformations, The method is based on the idea of using un-normed reflector vector. Results from experiments on the Intel Paragon are given. Comparison between the ScaLapack bidiagonalization and the method proposed is provided. (C) 1998 Elsevier Science B.V. All rights reserved.

关键词： linear algebra bidiagonal form householder transformation distributed memory architecture

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REDUCTION TO CONDENSED FORM FOR THE EIGENVALUE PROBLEM ON distributed memory architectureS

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PARALLEL COMPUTING 1992年第9期18卷 973-982页

作者： DONGARRA, JJ VANDEGEIJN, RA OAK RIDGE NATL LAB MATH SCI SECTOAK RIDGETN 37831 UNIV TEXAS DEPT COMP SCIAUSTINTX 78712

In this paper, we describe a parallel implementation for the reduction of general and symmetric matrices to Hessenberg and tridiagonal form, respectively. The methods are based on LAPACK sequential codes and use a pan... 详细信息

关键词： EIGENVALUE PROBLEM LINEAR ALGEBRA LAPACK distributed memory architecture

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A parallel divide and conquer algorithm for the symmetric eigenvalue problem on distributed memory architectures

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SIAM JOURNAL ON SCIENTIFIC COMPUTING 1999年第6期20卷 2223-2236页

作者： Tisseur, F Dongarra, J Univ Manchester Dept Math Manchester M13 9PL Lancs England Univ Tennessee Dept Comp Sci Knoxville TN 37996 USA Oak Ridge Natl Lab Math Sci Sect Oak Ridge TN 37831 USA

We present a new parallel implementation of a divide and conquer algorithm for computing the spectral decomposition of a symmetric tridiagonal matrix on distributed memory architectures. The implementation we develop differs from other implementations in that we use a two-dimensional block cyclic distribution of the data, we use the Lowner theorem approach to compute orthogonal eigenvectors, and we introduce permutations before the back transformation of each rank-one update in order to make good use of deflation. This algorithm yields the first scalable, portable, and numerically stable parallel divide and conquer eigensolver. Numerical results confirm the effectiveness of our algorithm. We compare performance of the algorithm with that of the QR algorithm and of bisection followed by inverse iteration on an IBM SP2 and a cluster of Pentium PIIs.

关键词： divide and conquer symmetric eigenvalue problem tridiagonal matrix rank-one modification parallel algorithm ScaLAPACK LAPACK distributed memory architecture

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OpenMP compiler for distributed memory architectures

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Science China(Information Sciences) 2010年第5期53卷 932-944页

作者： WANG Jue , HU ChangJun, ZHANG JiLin & LI JianJiang School of Information and Engineering, University of Science and Technology Beijing, Beijing 100083, China 1. School of Information and Engineering University of Science and Technology Beijing Beijing 100083 China

OpenMP is an emerging industry standard for shared memory architectures. While OpenMP has advantages on its ease of use and incremental programming, message passing is today still the most widely-used programming model for distributed memory architectures. How to effectively extend OpenMP to distributed memory architectures has been a hot spot. This paper proposes an OpenMP system, called KLCoMP, for distributed memory architectures. Based on the "partially replicating shared arrays" memory model, we propose an algorithm for shared array recognition based on the inter-procedural analysis, optimization technique based on the producer/consumer relationship, and communication generation technique for nonlinear references. We evaluate the performance on nine benchmarks which cover computational fluid dynamics, integer sorting, molecular dynamics, earthquake simulation, and computational chemistry. The average scalability achieved by KLCoMP version is close to that achieved by MPI version. We compare the performance of our translated programs with that of versions generated for Omni+SCASH, LLCoMP, and OpenMP(Purdue), and find that parallel applications (especially, irregular applications) translated by KLCoMP can achieve more effective performance than other versions.

关键词： parallel compiling high performance computing distributed memory architecture OpenMP irregular application

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Evaluation of Synchronous Dataflow Graph Mappings onto distributed memory architectures. 19

Evaluation of Synchronous Dataflow Graph Mappings onto Distr...

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19th Euromicro Conference on Digital System Design (DSD)

作者： Lesparre, Youen Munier-Kordon, Alix Delosme, Jean-Marc Univ Paris 06 Sorbonne Univ CNRS LIP6 Paris France Univ Evry Val dEssonne IBISC F-91025 Evry France

ISBN: (纸本)9781509028160

The search of a mapping of a Synchronous Data Flow Graph (SDFG) on a distributed architecture that achieves a given throughput while satisfying memory constraints is a difficult challenge. Solving this problem calls for evaluating throughput and buffer capacities associated to a mapping. Since the available mapping evaluation methods are not polynomial with respect to the SDFG description, mapping techniques using them are not scalable. This paper develops a polynomial method for the evaluation of any given SDFG mapping on a distributed architecture. The method is based on a simple transformation of the SDFG to model communications through a Network on Chip. The key result is that the size of the memory required in order to guarantee the liveness or a given throughput of an application may be evaluated in polynomial time. Experimentally, computing the memory size guaranteeing liveness of a mapping of a 670-node H264 graph on a 4-cluster architecture takes 70 ms on an Intel Core i5-660 processor and grows linearly with graph size.

关键词： distributed memory architecture Liveness Mapping Synchronous Dataflow Graph Throughput Constraint

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