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Coupling multicomponent models with MPH on distributed memory computer architectures

INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2005年第3期19卷 329-340页

作者： He, Y Ding, CHQ Univ Calif Berkeley Lawrence Berkeley Lab Computat Res Div Berkeley CA 94720 USA

A growing trend in developing large and complex applications on today's Teraflop-scale computers is to integrate standalone and/or semi-independent program components into a comprehensive simulation package. One example is the Community Climate System Model, which consists of atmosphere, ocean, land-surface, and sea ice components. Each component is semi-independent and has been developed at a different institution. We study how this multicomponent, multi-executable application can run effectively on distributed memory architectures. For the first time, we clearly identify five effective execution modes and develop the MPH library to support application development utilizing these modes. MPH performs component-name registration, resource allocation and initial component handshaking in a flexible way.

关键词： multicomponent multi-executable component integration distributed memory architecture climate modeling Community Climate System Model Parallel Climate Model

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Parallelization and Optimization of a CAD Model Processing Tool from the Automotive Industry to distributed memory Parallel Computers 11th

Parallelization and Optimization of a CAD Model Processing T...

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11th International Conference on Parallel Processing and Applied Mathematics (PPAM)

作者： Ayuso, Luis Durillo, Juan J. Kornberger, Bernhard Schifko, Martin Fahringer, Thomas Univ Innsbruck Inst Comp Sci Innsbruck Austria Geom Softwareentwicklung Graz Austria ESS Engn Software Steyr GmbH Munich Germany

ISBN: (纸本)9783319321493;9783319321486

In the early phases of an automotive industry development, design time can be substantially improved by using automated tools that assist engineers to perform repetitive and time consuming tasks, speeding up automotive products development and providing quality guarantees over otherwise error-prone processes. MERGE is such a tool from industry that prepares CAD models for electrophoretic deposition simulation. In this paper we describe the parallelization and optimization of MERGE for distributed memory parallel architectures. For this purpose we create a dynamic tree of tasks at runtime, analyze its load behavior and execute it through a master-worker compute paradigm based on different scheduling policies. Our implementation is based on a hybrid MPI-OpenMP version which results in a considerable improvement of both resource utilization and performance. Empirical performance results are presented for our new approach which achieve a speedup of up to 18 on an SMP cluster architecture.

关键词： distributed memory architecture MPI-OpenMP CAD Intree precedence Task scheduling

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A distributed IMPLEMENTATION OF SHARED VIRTUAL memory WITH STRONG AND WEAK COHERENCE 2nd

A DISTRIBUTED IMPLEMENTATION OF SHARED VIRTUAL MEMORY WITH S...

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2ND EUROPEAN CONF ON distributed memory COMPUTING ( EDMCC2 )

作者： GILOI, WK HASTEDT, C SCHOEN, F SCHROEDERPREIKSCHAT, W GMD Research Center for Innovative Computer Systems and Technology Technical University of Berlin Germany

ISBN: (纸本)3540539514

A virtual shared memory architecture (VSMA) is a distributed memory architecture that looks to the application software as if it were a shared memory system. The major problem with such a system is to maintain the coherence of the distributed data entities. Shared virtual memory means that the shared data entities are pages of local virtual memories with demand paging. memory coherence may be strong or weak. Strong coherence is a scheme where all the shared data entities look from the outside as if they were stored in one coherent memory. This simplifies programming of a distributed memory system at the cost of a high message traffic in the system, needed to maintain the strong coherence. The efficiency of the system can be increased by adding a weak coherence scheme that allows for multiple writes by different threads of control into the same page. The price of the weak coherence scheme is the need for explicit program synchronizations, needed to reestablish at the end the strong coherence of the result. For the computer architect, the challenging question is how to implement a VSMA most efficiently and, specifically, by what architectural means to support the implementation. In the paper a new solution to this question is presented based upon an innovative distributed memory architecture in which communication is conducted by a dedicated communication processor in each node rather than by the node CPU. This will make the exchange of short, fixed-size messages, e.g., invalidation notices, very efficient. Therefore, it becomes more appropriate to minimize the overall administrative overhead, even at the cost of more message traffic. On that rationale, a novel, capability-based mechanism for both strong and weak coherence of shared virtual memory is presented. The weak coherence scheme is built on top of the strong coherence, utilizing its mechanisms. The proposed implementation is totally distributed and based on a strict need to know philosophy. Consequently, the e

关键词： distributed memory architecture VIRTUAL SHARED memory architecture STRONG AND WEAK DATA COHERENCE COMMUNICATION HARDWARE PARALLELIZING COMPILERS

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A distributed memory Parallel Fourth-Order IADEMF Algorithm

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INTERNATIONAL JOURNAL OF ADVANCED COMPUTER SCIENCE AND APPLICATIONS 2019年第9期10卷 599-607页

作者： Abu Mansor, Noreliza Zulkifle, Ahmad Kamal Alias, Norma Hasan, Mohammad Khatim Univ Tenaga Nas Coll Engn Selangor Malaysia Univ Teknol Malaysia Ibnu Sina Inst Fundamental Sci Studies Johor Baharu Malaysia Univ Kebangsaan Malaysia Fac Informat Sci & Technol Bangi Malaysia

The fourth-order finite difference Iterative Alternating Decomposition Explicit Method of Mitchell and Fairweather (IADEMF4) sequential algorithm has demonstrated its ability to perform with high accuracy and efficiency for the solution of a one-dimensional heat equation with Dirichlet boundary conditions. This paper develops the parallelization of the IADEMF4, by applying the Red-Black (RB) ordering technique. The proposed IADEMF4-RB is implemented on multiprocessor distributed memory architecture based on Parallel Virtual Machine (PVM) environment with Linux operating system. Numerical results show that the IADEMF4-RB accelerates the convergence rate and largely improves the serial time of the IADEMF4. In terms of parallel performance evaluations, the IADEMF4-RB significantly outperforms its counterpart of the second-order (IADEMF2-RB), as well as the benchmarked fourth-order classical iterative RB methods, namely, the Gauss-Seidel (GS4-RB) and the Successive Over-relaxation (SOR4-RB) methods.

关键词： Fourth-order method finite difference red-black ordering distributed memory architecture parallel performance evaluations

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Parallel architectures for processing high speed network signaling protocols

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IEEE-ACM TRANSACTIONS ON NETWORKING 1995年第6期3卷 716-728页

作者： Ghosal, D Lakshman, TV Huang, YN AT&T BELL LABS HOLMDELNJ 07733 AT&T BELL LABS MURRAY HILLNJ 07974

We study the effectiveness of different parallel architectures for achieving the high throughputs and low latencies needed in processing signaling protocols for high speed networks. A key performance issue is the trade off between the load balancing gains and the call record management overhead. Arranging processors in large groups potentially yields higher load balancing gains but also incurs higher overhead in maintaining consistency among the replicated copies of the cad records. We study this tradeoff and its impact on the design of protocol processing systems for two generic classes of parallel architectnres, namely, shared memory and distributed memory architectures. In shared memory architectures, maintaining a common message queue in the shared memory can provide the maximal load balancing gains. We show, however, in order to optimize performance it is necessary to organize the processors in small groups since large groups result in higher cad record management overhead In distributed memory architectures with each processor maintaining its own message queue there is no inherent provision for load balancing, Based on a detailed simulation analysis we show that organizing the processors into small groups end using a simple distributed load balancing scheme yields modest performance gains even after cap record management overheads are taken into account, We find that the common message queue architecture outperforms the distributed architecture in terms of lower response time due to its improved load balancing capability, Finally, we do a fault-tolerance analysis with respect to the call-record data structure, Using a simple failure recovery model of the processors and the local memory, we show that in the case of shared memory architecture, the availability is also optimized when processors are organized in small groups, This is because when comparing architectures the higher cap record management overhead incurred for larger group sizes must be accounted for

关键词： Parallel architectures Telecommunication Networks Telecommunication Computing Signal Processing memory architecture Shared memory Systems distributed memory Systems Telecommunication Network Reliability Transport Protocols Parallel architectures High Speed Network Signaling Protocols High Throughputs Low Latencies Signaling Protocols Processing Load Balancing Gains Call Record Management Overhead Protocol Processing Systems distributed memory architecture Shared memory architecture Message Queue Performance Optimisation Simulation Analysis distributed Load Balancing Message Queue architecture Response Time Fault Tolerance Analysis Call Record Data Structure Failure Recovery Model Local memory Availability System Unavailability Parallel architectures High Speed Networks Signal Processing Load Management memory architecture Delay Protocols Performance Gain Throughput Process Design

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Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework

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IEEE ACCESS 2024年 12卷 124081-124094页

作者： Pudi, Dhilleswararao Malviya, Shivam Boppu, Srinivas Yang, Yu Hemani, Ahmed Cenkeramaddi, Linga Reddy Indian Inst Technol Bhubaneswar Sch Elect Sci Bhubaneswar 752050 India KTH Royal Inst Technol Div Elect & Embedded Syst Stockholm S-11428 Sweden Univ Agder Dept ICT N-4630 Grimstad Norway

Coarse-Grained Reconfigurable Array (CGRA) architectures are potential high-performance and power-efficient platforms. However, mapping applications efficiently on CGRA, which includes scheduling and binding operations on functional units and variables on registers, is a daunting problem. SiLago is a recently developed VLSI design framework comprising two large-scale reconfigurable fabrics: Dynamically Reconfigurable Resource Array (DRRA) and distributed memory architecture (DiMArch). It uses the Vesyla compiler to map applications on these fabrics. The present version of Vesyla executes binding and scheduling sequentially, with binding first, followed by scheduling. In this paper, we proposed an Integer Linear Programming (ILP)-based exact method to solve scheduling and binding simultaneously that delivers better solutions while mapping applications on these fabrics. The proposed ILP combines two objective functions, one for scheduling and one for binding, and both of these objective functions are coupled with weightage factors $\alpha $ and $\beta $ so that the user can have the flexibility to prioritize either scheduling or binding or both based on the requirements. We determined the binding and execution time of image processing tasks and various routines of the Basic Linear Algebraic Subprogram (BLAS) using the proposed ILP for multiple combinations of weightage factors. Furthermore, a comparison analysis has been conducted to compare the latency and power dissipation of several benchmarks between the existing and proposed approaches. The experimental results demonstrate that the proposed method exhibits a substantial reduction in power consumption and latency compared to the existing method.

关键词： Random access memory Radio frequency Registers Switches Dynamic scheduling Reconfigurable architectures distributed management memory management Integer linear programming Scheduling Power demand Coarse-grain reconfigurable architecture dynamically reconfigurable resource array distributed memory architecture integer linear programming high-level synthesis scheduling binding

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Parallel computing for efficient time-frequency feature extraction of power quality disturbances

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IET SIGNAL PROCESSING 2013年第4期7卷 312-326页

作者： Krishna, Brahmadesam V. Baskaran, Kaliaperumal Saranathan Coll Engn Dept CSE Thiruchirappalli 620012 India Govt Coll Technol Dept CSE Coimbatore 641013 Tamil Nadu India

Fast signal processing implementation techniques for detection and classification of power quality (PQ) disturbances are the need of the hour. Hence in this work, a parallel computing approach has been proposed to speed up the feature extraction of PQ signals to facilitate rapid building of classifier models. Considering that the Fourier, the one-dimensional discrete wavelet, the time-time and the Stockwell transforms have been used extensively to extract pertinent time-frequency features from non-stationary and multi-frequency PQ signals, acceleration approaches using data and task parallelism have been employed for parallel implementation of the above time-frequency transforms. In the first approach, data parallelism was applied to the Stockwell transform and the time-time transform-based feature extraction methods separately to alleviate capability problems. Also, data parallelism was applied to Fourier and wavelet-based feature extraction methods independently to alleviate capacity problems. Secondly, a combination of task and data parallelism was applied to speed up S-transform based three-phase sag feature extraction. Experiments were conducted using shared-memory and distributed memory architectures to try out the effectiveness of the proposed parallel approaches. The performances of these parallel implementations were analysed in terms of computational speed and efficiency in comparison with the sequential approach.

关键词： discrete wavelet transforms distributed memory systems feature extraction Fourier transforms parallel memories parallel processing power engineering computing power supply quality power system faults shared memory systems signal classification signal detection time-frequency analysis time-frequency feature extraction parallel computing signal processing power quality disturbance classification power quality disturbance detection classifier model 1D discrete wavelet transform time-time transform multifrequency PQ signal nonstationary PQ signal acceleration approach data parallelism task parallelism time-frequency transform Stockwell transform Fourier transform S-transform sag feature extraction distributed memory architecture shared memory architecture discrete wavelet transforms distributed memory systems feature extraction Fourier transforms parallel memories parallel processing power engineering computing power supply quality power system faults shared memory systems signal classification signal detection time-frequency analysis time-frequency feature extraction parallel computing signal processing power quality disturbance classification power quality disturbance detection classifier model 1D discrete wavelet transform time-time transform multifrequency PQ signal nonstationary PQ signal acceleration approach data parallelism task parallelism time-frequency transform Stockwell transform Fourier transform S-transform sag feature extraction distributed memory architecture shared memory architecture

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Using accurate arithmetics to improve numerical reproducibility and stability in parallel applications

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JOURNAL OF SUPERCOMPUTING 2001年第3期18卷 259-277页

作者： He, Y Ding, CHQ Univ Calif Berkeley Lawrence Berkeley Lab NERSC Div Berkeley CA 94720 USA

Numerical reproducibility and stability of large scale scientific simulations, especially climate modeling, on distributed memory parallel computers are becoming critical issues. In particular, global summation of distributed arrays is most susceptible to rounding errors, and their propagation and accumulation cause uncertainty in final simulation results. We analyzed several accurate summation methods and found that two methods are particularly effective to improve (ensure) reproducibility and stability: Kahan's self-compensated summation and Bailey's double-double precision summation. We provide an MPI operator MPI_SUMDD to work with MPI collective operations to ensure a scalable implementation on large number of processors. The final methods are particularly simple to adopt in practical codes: not only global summations, but also vector-vector dot products and matrix-vector or matrix-matrix operations.

关键词： reproducibility climate models double-double precision arithmetic self-compensated summation distributed memory architecture

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Multifrontal parallel distributed symmetric and unsymmetric solvers

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COMPUTER METHODS IN APPLIED MECHANICS AND ENGINEERING 2000年第2-4期184卷 501-520页

作者： Amestoy, PR Duff, IS L'Excellent, JY IRIT ENSEEIHT Toulouse France Rutherford Appleton Lab Didcot OX11 0QX Oxon England CERFACS F-31057 Toulouse France

We consider the solution of both symmetric and unsymmetric systems of sparse linear equations. A new parallel distributed memory multifrontal approach is described. To handle numerical pivoting efficiently, a parallel asynchronous algorithm with dynamic scheduling of the computing tasks has been developed. We discuss some of the main algorithmic choices and compare both implementation issues and the performance of the LDLT and LU factorizations. Performance analysis on an IBM SP2 shows the efficiency and the potential of the method. The test problems used are from the Rutherford-Boeing collection and from the PARASOL end users. (C) 2000 Elsevier Science S.A. All rights reserved.

关键词： MPI distributed memory architecture sparse matrices multifrontal direct methods

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Wavelet packet best basis selection on moderate parallel MIMD architectures

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PARALLEL COMPUTING 1996年第1期22卷 149-158页

作者： Uhl, A SALZBURG UNIV DEPT COMP SCI & SYST ANALA-5020 SALZBURGAUSTRIA

Wavelet packet best basis selection has become a popular method in image compression. This paper introduces a subband based parallelization which overcomes most of the difficulties of a straightforward parallel version of the sequential algorithm. Beside the higher efficiency the algorithm is easier to implement than its classical version.

关键词： image compression wavelet transform distributed memory architecture parallel wavelet packet decomposition best basis selection

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