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Lana-Match algorithm: a parallel version of the Rete-Match algorithm

PARALLEL COMPUTING 1998年第5-6期24卷 763-775页

作者： Aref, MM Tayyib, MA King Fahd Univ Petr & Minerals Dept Informat & Comp Sci Dhahran 31261 Saudi Arabia

The Rete-Match algorithm is a matching algorithm used to develop production systems. Although this algorithm is the fastest known algorithm, for many patterns and many objects matching, it still suffers from considerable amount of time needed due to the recursive nature of the problem. In this paper, a parallel version of the Rete-Match algorithm for distributed memory architecture is presented. Also, a theoretical analysis to its correctness and performance is discussed. (C) 1998 Elsevier Science B.V. All rights reserved.

关键词： distributed memory architecture Rete-Match algorithm performance correctness analysis production systems

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A New Progressive Algorithm for a Multiple Longest Common Subsequences Problem and Its Efficient Parallelization

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IEEE TRANSACTIONS ON PARALLEL AND distributed SYSTEMS 2013年第5期24卷 862-870页

作者： Yang, Jiaoyun Xu, Yun Sun, Guangzhong Shang, Yi Univ Sci & Technol China Key Lab High Performance Comp Hefei 230027 Anhui Peoples R China Univ Sci & Technol China Sch Comp Sci Hefei 230027 Anhui Peoples R China Univ Missouri Dept Comp Sci Columbia MO 65211 USA

The multiple longest common subsequence (MLCS) problem, which is related to the measurement of sequence similarity, is one of the fundamental problems in many fields. As an NP-hard problem, finding a good approximate solution within a reasonable time is important for solving large-size problems in practice. In this paper, we present a new progressive algorithm, Pro-MLCS, based on the dominant point approach. Pro-MLCS can find an approximate solution quickly and then progressively generate better solutions until obtaining the optimal one. Pro-MLCS employs three new techniques: 1) a new heuristic function for prioritizing candidate points;2) a novel d-index-tree data structure for efficient computation of dominant points;and 3) a new pruning method using an upper bound function and approximate solutions. Experimental results show that Pro-MLCS can obtain the first approximate solution almost instantly and needs only a very small fraction, e. g., 3 percent, of the entire running time to get the optimal solution. Compared to existing state-of-the-art algorithms, Pro-MLCS can find better solutions in much shorter time, one to two orders of magnitude faster. In addition, two parallel versions of Pro-MLCS are developed: DPro-MLCS for distributed memory architecture and DSDPro-MLCS for hierarchical distributed shared memory architecture. Both parallel algorithms can efficiently utilize parallel computing resources and achieve nearly linear speedups. They also have a desirable progressiveness property-finding better solutions in shorter time when given more hardware resources.

关键词： Multiple longest common subsequence problem (MLCS) skyline problem branch-and-bound search progressive algorithm distributed memory architecture SMP cluster

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architectureS WITHIN THE ESPRIT SPAN PROJECT

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IEEE MICRO 1990年第6期10卷 24-&页

作者： ROUNCE, P DELGADO, J INST SUPER TECN LISBON 1PORTUGAL INST ENGN SIST & COMP LISBONPORTUGAL

An overview is given of the SPAN project, which pooled the resources of numerous researchers in several countries to integrate symbolic and numeric computing on parallel systems. The resulting Kernel System architectures provided a central model for which two programming languages and two parallel-system architectures were developed. The Kernel System architecture, Parle high-level procedural language, Virtual Machine Code, Sprint processor architecture, and DICE distributed memory architecture are examined.

关键词： architecture Computer Programming Languages Building construction procedural language Building systems memory architecture distributed memory architecture

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Parallel execution of Prolog with granularity control

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 1998年第6期13卷 421-441页

作者： Araujo, L Ruz, JJ Univ Complutense Madrid Dipartimento Automat & Informat E-28040 Madrid Spain

This paper presents a system for parallel execution of Prolog supporting both independent conjunctive and disjunctive parallelism. The system is intended for distributed memory architecture and is composed of a set of workers with a hierarchical structure scheduler. The execution model has been designed in such a way that each worker's environment does not contain references to terms in other environments, thus reducing communication overhead. In order to guarantee the improvement of the performance by the parallelism exploitation, a granularity control has been introduced for each kind of parallelism. For conjunctive parallelism PDP applies a control based on the estimation provided by CASLOG. The features of the system allow to introduce this control without adding overhead. For disjunctive parallelism PDP controls granularity by applying a heuristic-based method, which can be adapted to other parallel Prolog systems. Different scheduling policies have also been tested. The system has been implemented on a transputer network and performance results show that it provides a high speedup for coarse grain parallel programs. (C) 1998 Elsevier Science B.V.

关键词： logic programming conjunctive parallelism disjunctive parallelism granularity distributed memory architecture

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Automating functional unit and register binding for synchoros CGRA platform

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DESIGN AUTOMATION FOR EMBEDDED SYSTEMS 2024年第2期28卷 155-186页

作者： Pudi, Dhilleswararao Tiwari, Utsav Boppu, Srinivas Yang, Yu Hemani, Ahmed Indian Inst Technol Bhubaneswar IITBBS Sch Elect Sci Bhubaneswar 752050 Odisha India Royal Inst Technol KTH Sch Elect Engn & Comp Sci Kistagangen 16 S-16440 Stockholm Sweden

Coarse-grain reconfigurable architectures, which provide high computing throughput, low cost, scalability, and energy efficiency, have grown in popularity in recent years. SiLago is a new VLSI design framework comprised of two coarse-grain reconfigurable fabrics: a dynamically reconfigurable resource array and a distributed memory architecture. It employs the Vesyla compiler to map streaming applications on these fabrics. Binding is a critical step in the high-level synthesis that maps operations and variables to functional units and storage elements in the design. It influences design performance metrics such as power, latency, area, etc. The current version of Vesyla does not support automatic binding, and it has to be specified manually through pragmas, which makes it less flexible. This paper proposes various approaches to automate the binding in Vesyla. We present a list scheduling-based approach to automate functional unit binding and an integer linear programming approach to automate register binding. Furthermore, we determine the binding of various basic linear algebraic subprogram and image processing tasks using the proposed approaches. Finally, a comparative analysis has been made between the automatic and manual binding concerning the power dissipation and latency for various benchmarks. The experimental results show that the proposed automatic binding consumes significantly less power for nearly the same latency as manual binding.

关键词： High-level synthesis Coarse-grain reconfigurable architecture Binding SiLago Vesyla Integer linear programming Dynamically reconfigurable resource array distributed memory architecture

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THE SUPRENUM SUPERCOMPUTER - GOALS, ACHIEVEMENTS, AND LESSONS LEARNED

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PARALLEL COMPUTING 1994年第1-11期20卷 1407-1425页

作者： GILOI, WK GMD Institute for Computer Architecture and Software Technology Rudower Chausses 5 D-12489 Berlin Germany

SUPRENUM is a highly parallel supercomputer for numerical applications. The 5-GFLOPS peak performance of the 256-node system made it the most powerful MIMD architecture of the 'first generation.' Each node is a complete, single-board vector machine with 20 Mflops peak performance (IEEE double precision). SUPRENUM is a distributed memory architecture, resulting in a highly scalable system that can be made fault-tolerant. Message passing is accelerated by dedicated communication hardware in each node. Array access is performed by an 'intelligent' DMA address generator. The SUPRENUM architecture was the first to be based on two-level interconnection structure, consisting of a number of clusters with each cluster consisting of a number of nodes. At the cluster level the nodes are interconnected by two very fast parallel buses. At the system level the clusters are interconnected by a torus structure consisting of serial ring buses. The nodes run under the proprietary, distributed PEACE operating system. Significant efforts were undertaken to make the system programmable, by providing a host of software tools, libraries, and application software packages. The paper discusses the rationale for the SUPRENUM architecture, the goals achieved, and the lessons learned.

关键词： distributed memory architecture VECTOR NODES HIERARCHICAL INTERCONNECTION STRUCTURE distributed OPERATING SYSTEM PROGRAMMING PARADIGMS AND TOOLS

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IMPLEMENTING LINDA TUPLESPACE ON A distributed SYSTEM

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INTERNATIONAL JOURNAL OF HIGH SPEED COMPUTING 1995年第1期7卷 125-144页

作者： FENG, MD GAO, YQ YUEN, CK Department of Information Systems and Computer Science National University of Singapore Kent Ridge Singapore 0511 Singapore On leave from National University of Singapore and his current address: Department of Information Science University of Tokyo 7-3-1 Hongo Bunkyo-ku 113 Tokyo Japan.

Linda, a general purpose coordination language, has been used to make a language parallel. Based on a logically shared tuplespace, Linda poses difficulties to be efficiently implemented on a distributed multiprocessor system. This paper reports our approach to solve the problem: processors are divided into groups, and each group has a group manager to provide a local view of the global tuplespace, and handles the tuplespace operations incurred by processors within the group. To maintain the consistency and correctness of the Linda tuplespace operations, we propose the algorithms of a group manager. We also implement the algorithms on a transputer-based multicomputer and show the experiment results.

关键词： TUPLESPACE CONSISTENCY distributed memory architecture GROUPING

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Efficient Implementation of 2-D Convolution on DRRA and DiMArch architectures 23

Efficient Implementation of 2-D Convolution on DRRA and DiMA...

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13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

作者： Pudi, Dhilleswararao Ryansh, Rajeev Boppu, Srinivas Yang, Yu Hemani, Ahmed Indian Inst Technol Bhubaneswar Odisha India Royal Inst Technol KTH Kista Sweden

ISBN: (纸本)9798400700439

Convolution has been widely employed in image processing and computer vision applications such as picture augmentation, smoothing, and structure extraction. In addition, convolution operations are the most prevalent computing patterns in machine learning domains. Convolutions, for example, are used in a substantial chunk of state-of-the-art convolutional neural network operations. Therefore, effectively mapping convolution operations onto hardware architectures is crucial for achieving superior performance while accelerating convolutional neural networks. In this paper, we proposed various algorithms to efficiently map the 2-D convolution operation onto a dynamically reconfigurable resource array and distributed memory architecture. Furthermore, we have discussed the mapping of 2-D convolution on the target architecture for an input matrix of arbitrary size, as well as the generalization of the proposed approaches for multi-column DRRA architectures.

关键词： Convolution Coarse Grain Reconfigurable architectures Dynamically Reconfigurable Resource Array distributed memory architecture Machine Learning Convolutional Neural Networks FPGA

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Implementation of Image Averaging on DRRA and DiMArch architectures 36

Implementation of Image Averaging on DRRA and DiMArch Archit...

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36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Pudi, Dhilleswararao Goudu, Vamsi Boppu, Srinivas Ratnu, Ritika Hemani, Ahmed Indian Inst Technol Bhubaneswar Bhubaneswar India KTH Royal Inst Technol Stockholm Sweden

ISBN: (纸本)9798350318340

Image averaging is a technique used in image processing to reduce the noise present in an image. Image averaging is computationally intensive, particularly when dealing with images with high resolutions and large sizes. Thus, employing specialized hardware, such as field programmable gate arrays and coarse-grained reconfigurable architectures, becomes essential for efficient implementations, surpassing the capability of general-purpose processors. This paper proposes various approaches for implementing image averaging using two coarse-grain reconfigurable fabrics: dynamically reconfigurable resource array and distributed memory architecture. Furthermore, we have discussed the implementation of image averaging on the target architecture for an input matrix of arbitrary size. Finally, the proposed approaches were compared with a field-programmable gate array-based implementation in terms of power dissipation. The experimental results show that the proposed approaches consume considerably less power than a field-programmable gate array-based implementation.

关键词： Image averaging Coarse-grained reconfigurable architectures Dynamically reconfigurable resource array distributed memory architecture

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A Fast Wavelet Packet Transform-based algorithm for numerical solution of image restoration problems in a parallel environment

A Fast Wavelet Packet Transform-based algorithm for numerica...

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Conference on Wavelet Applications in Signal and Image Processing VI

作者： Carracciuolo, L D'Amore, L Murli, A Univ Naples Federico II Naples Italy

ISBN: (纸本)0819429139

We explore the filtering properties of wavelets functions in order to develop accurate and efficient numerical algorithms for Image Restoration problems. We propose a parallel implementation for MIMD distributed memory environments. The key insight of our approach is the use of distributed versions of Level 3 Basic Linear Algebra Subprograms as computational building blocks and the use of Basic Linear Algebra Communication Subprograms las communication building blocks for advanced architecture computers. The use of these low-level mathematical software libraries garantees the development of efficient, portable and scalable high-level algorithms and hides many details of the parallelism from the user's point of view. Numerical experiments on a simulated image restoration applications are shown. The parallel software has been tested on a 12 nodes IBM SP2 available at the Center for Research on Parallel Computing and Supercomputers in Naples (Italy).

关键词： Image Restoration preconditioning regularization wavelets parallel implementation distributed memory architecture

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