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The application of static load balancers in parallel compositional reservoir simulation on distributed memory system

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JOURNAL OF NATURAL GAS SCIENCE AND ENGINEERING 2016年 28卷 447-460页

作者： Guo, Xuyang Wang, Yuhe Killough, John Texas A&M Univ Harold Vance Dept Petr Engn 3116 TAMU College Stn TX 77843 USA Petr Engn Program Texas A&M Engn BldgEduc CityPOB 23874 Doha Qatar

Compositional reservoir simulation depicts the complex behaviors of all the components in gaseous, liquid, and oil phases. It helps to understand the dynamic changes in reservoirs. Parallel computing is implemented to speed up simulation in large scale fields. However, there is still many challenges in obtaining efficient and cost-effective parallel reservoir simulation. Load imbalance on processors in the parallel machine is a major problem and it severely affects the performance of parallel implementation in compositional reservoir simulators. This article presents a new approach to the reduction of load imbalance among processors in large scale parallel compositional reservoir simulation. The approach is based on graph partitioning techniques: Metis partitioning and spectral partitioning. These techniques treat the simulation grid, or the mesh, as a graph constituted by vertices and edges, and then partition the graph into smaller domains. Metis and spectral partitioning techniques are advantageous because they take into account the potential computational load of each grid block in the mesh and generate smaller partitions for heavy computational load areas and larger partitions for light computational load areas. In our case, the computational load is represented by transmissibility. After new partitions are generated, each of them is assigned to a processor in the parallel machine and new parallel reservoir simulation can be conducted. Traditionally, the intuitive 2D decomposition is frequently used to partition the simulation grid into small rectangles, and this is a major source of load imbalance. The performance of parallel compositional simulation based on our partitioning techniques is compared with the most commonly used 2D decomposition and it is found that load imbalance in our new simulations is reduced when compared with the traditional 2D decomposition. This study improves the efficiency of compositional simulation and eventually makes it more cost-e

关键词： Compositional reservoir simulation High performance computing Load balance Graph partitioning distributed memory system

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Parallel multi-level fast multipole algorithm with combined field integral equation on distributed memory system

Parallel multi-level fast multipole algorithm with combined ...

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Asia-Pacific Microwave Conference

作者： Lin Yun Hun Jun Nie Zai Ping Chen Yong Pin Univ Elect Sci & Technol China Coll Elect Engn Chengdu 610054 Sichuan Peoples R China

ISBN: (纸本)078039433X

Although the multilevel fast multipole algorithm (MLFMA) has been the most popular method in electromagnetic field computation, the limitation of both CPU speed and memory size make it still difficult to solve the scattering problems from very large scale structures using this method. In this paper, we implemented the CFIE (combined filed integral equation) into our Parallel MLFMA solving the electromagnetic scattering problem of an electrical-large PEC targets on the Message Passing Interface (MPI) in a cluster system. A lot of numerical results are represented in this paper. From the numerical result presented a very good convergence speed is achieved, and the scattering from a very large scale problem which has about 1 million unknowns is solved. Finally, the result is presented and discussed in this paper.

关键词： scattering Integral Equation RCS parallel MLFMA distributed memory system

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Scalable distributed memory embedded system with a low-cost hardware message passing interface

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IEICE ELECTRONICS EXPRESS 2009年第12期6卷 837-843页

作者： Jeong, Ha-young Hur, Won Lee, Yong-surk Yonsei Univ Sch Elect & Elect Engn Processor Lab Seoul 120749 South Korea

In this paper, we propose a scalable distributed memory system with a low-cost hardware message-passing interface. The proposed interface improves the communication performance between nodes to decrease the overhead synchronization with a receiver reservation technique. The simulation results indicate that the performance is increased by 20% on 4x4 communications. The synthesis result of the proposed MPI indicates that the area was only 4.49% of each computing node. As a result, the proposed system is a useful embedded MPSoCs (Multiprocessor system on a Chip) for its low-cost implementation and scalability.

关键词： distributed memory system MPSoC multiprocessor message-passing interface

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Fast and highly scalable parallel computations for fundamental matrix problems on distributed memory systems

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JOURNAL OF SUPERCOMPUTING 2010年第3期54卷 271-297页

作者： Li, Keqin SUNY Albany Dept Comp Sci New Paltz NY 12561 USA

We present fast and highly scalable parallel computations for a number of important and fundamental matrix problems on distributed memory systems (DMS). These problems include matrix multiplication, matrix chain product, and computing the powers, the inverse, the characteristic polynomial, the determinant, the rank, the Krylov matrix, and an LU- and a QR-factorization of a matrix, and solving linear systems of equations. Our highly scalable parallel computations for these problems are based on a highly scalable implementation of the fastest sequential matrix multiplication algorithm on DMS. We show that compared with the best known parallel time complexities on parallel random access machines (PRAM), the most powerful but unrealistic shared memory model of parallel computing, our parallel matrix computations achieve the same speeds on distributed memory parallel computers (DMPC), and have an extra polylog factor in the time complexities on DMS with hypercubic networks. Furthermore, our parallel matrix computations are fully scalable on DMPC and highly scalable over a wide range of system size on DMS with hypercubic networks. Such fast (in terms of parallel time complexity) and highly scalable (in terms of our definition of scalability) parallel matrix computations were rarely seen before on any distributed memory systems.

关键词： Cost optimality distributed memory parallel computer distributed memory system Hypercubic network Matrix computation Scalability Speedup

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Analysis of parallel algorithms for matrix chain product and matrix powers on distributed memory systems

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IEEE TRANSACTIONS ON PARALLEL AND distributed systemS 2007年第7期18卷 865-878页

作者： Li, Keqin SUNY Albany Dept Comp Sci New Paltz NY 12561 USA

Given N matrices A(1,) A(2,...,) A(N) of size N x N, the matrix chain product problem is to compute A(1) x A(2) x... x A(N). Given an N x N matrix A, the matrix powers problem is to calculate the first N powers of A, that is, A, A(2), A(3),... A(N). We solve the two problems on distributed memory systems (DMSs) with p processors that can support one-to-one communications in T(p) time. Assume that the fastest sequential matrix multiplication algorithm has time complexity O(N-alpha), where the currently best value of alpha is less than 2.3755. Let p be arbitrarily chosen in the range 1 <= p <= N alpha+1/(log N)(2). We show that the two problems can be solved by a DMS with p processors in T-chain (N, p) = [GRAPHICS] and [GRAPHICS] times, respectively, where the function log(+) is defined as follows: log(+) x = log x if x >= 1 and log(+) x = 1 if 0 < x < 1. We also give instantiations of,the above results on several typical DMSs and show that computing matrix chain product and matrix powers are fully scalable on distributed memory parallel computers (DMPCs), highly scalable on DMSs with hypercubic networks, and not highly scalable on DMSs with mesh and torus networks.

关键词： cost optimality distributed memory parallel computer distributed memory system dynamic processor allocation hypercubic network matrix chain product matrix multiplication matrix power mesh scalability speedup torus

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Power profiling of Cholesky and QR factorizations on distributed memory systems

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COMPUTER SCIENCE-RESEARCH AND DEVELOPMENT 2014年第2期29卷 139-147页

作者： Bosilca, George Ltaief, Hatem Dongarra, Jack Univ Tennessee Innovat Comp Lab Knoxville TN 37996 USA KAUST Supercomp Lab Thuwal Saudi Arabia

This paper presents the power profile of two high performance dense linear algebra libraries on distributed memory systems, ScaLAPACK and DPLASMA. From the algorithmic perspective, their methodologies are opposite. The former is based on block algorithms and relies on multithreaded BLAS and a two-dimensional block cyclic data distribution to achieve high parallel performance. The latter is based on tile algorithms running on top of a tile data layout and uses fine-grained task parallelism combined with a dynamic distributed scheduler (DAGuE) to leverage distributed memory systems. We present performance results (Gflop/s) as well as the power profile (Watts) of two common dense factorizations needed to solve linear systems of equations, namely Cholesky and QR. The reported numbers show that DPLASMA surpasses ScaLAPACK not only in terms of performance (up to 2X speedup) but also in terms of energy efficiency (up to 62 %).

关键词： Power profile analysis Dense linear algebra distributed memory system Dynamic scheduler

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Evaluation of Hierarchical Pincers Attack Search on distributed memory systems 6

Evaluation of Hierarchical Pincers Attack Search on Distribu...

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6th International Symposium on Computing and Networking (CANDAR) - Across Practical Development and Theoretical Research

作者： Nakamura, Asuka Tominaga, Hirobumi Maekawa, Yoshitaka Chiba Inst Technol Narashino Chiba Japan Chiba Inst Technol Dept Comp Sci Narashino Chiba Japan

ISBN: (纸本)9781538691847

This paper evaluates a distributed memory parallel search algorithm based on hierarchical pincers attack search (HPAS). HPAS is a parallel tree search algorithm with depth first search that uses a master processor and some slave processors. This algorithm is efficient because it can implicitly share data frequently with all processors using shared memory. The communication overhead costs of HPAS on a distributed memory system will increase because of the need for frequent inter -processor communication. Thus, few studies have reported implementations of HPAS on a distributed memory system, and the effectiveness of this method is unclear. Therefore, this paper proposes an HPAS implementation method on a distributed memory system and evaluates its effectiveness. As a result of the evaluation, the maximum speedup ratio of the proposed method compared with the branch and hound method is approximately 52.78 times.

关键词： branch and bound method parallel search algorithm distributed memory system hierarchical pincers attack search

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distributed ALGORITHM FOR PARALLEL EDIT DISTANCE COMPUTATION

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COMPUTING AND INFORMATICS 2020年第4期39卷 757-779页

作者： Sadiq, Muhammad Umair Yousaf, Muhammad Murtaza Univ Punjab Punjab Univ Coll Informat Technol PUCIT Lahore Pakistan

The edit distance is the measure that quantifies the difference between two strings. It is an important concept because it has its usage in many domains such as natural language processing, spell checking, genome matching, and pattern recognition. Edit distance is also known as Levenshtein distance. Sequentially, the edit distance is computed by using dynamic programming based strategy that may not provide results in reasonable time when input strings are large. In this work, a distributed algorithm is presented for parallel edit distance computation. The proposed algorithm is both time and space efficient. It is evaluated on a hybrid setup of distributed and shared memory systems. Results suggest that the proposed algorithm achieves significant performance gain over the existing parallel approach.

关键词： Edit distance dynamic programming parallel computing distributed memory system MPI OpenMP speedup

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A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1999年第11期34卷 1608-1618页

作者： Suzuoki, M Kutaragi, K Hiroi, T Magoshi, K Okamoto, S Oka, M Ohba, A Yanamoto, Y Furuhashi, M Tanaka, M Yutaka, T Okada, T Nagamatsu, M Urakawa, Y Funyu, M Kunimatsu, A Goto, H Hashimoto, K Ide, N Murakami, H Ohtaguro, Y Aono, A Sony Comp Entertainment Inc Tokyo 1070052 Japan Toshiba Corp Semicond Co Kawasaki Kanagawa 210 Japan Toshiba Microelect Corp Kawasaki Kanagawa Japan

A 250-MHz microprocessor intended for home computer entertainment consists of a CPU core with 128-b multimedia extensions, two single-instruction, multiple-data (SIMD) very long instruction word (VLIW) vector processors containing ten floating-point multiplier accelerators and four floating-point dividers, an MPEG-2 decoder, a ten-channel direct memory access (DMA) controller, and other peripherals with 128-b internal buses on one die. The core is a two-way superscalar MIPS-compatible microprocessor with 16-kB scratch-pad RAM. Each vector processor is a five-way SIMD-VLIW architecture, which is tightly dedicated for specific applications about three-dimensional geometry calculation and physical simulation. A DMA controller connects between main memory and each professor's local memory to conceal memory access penalty. It contains 10.5 M transistors in 17 x 14.1 mm and dissipates 15 W at 1.8 V.

关键词： computer graphics data flow computing digital signal processing discrete cosine transform distributed memory system home computing image processing integrated circuit design multimedia systems multiprocessor interconnection real time systems

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Towards a more efficient implementation of OpenMP for clusters via translation to global arrays

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PARALLEL COMPUTING 2005年第10-12期31卷 1114-1139页

作者： Huang, L Chapman, B Liu, ZY Univ Houston Dept Comp Sci Houston TX 77204 USA

This paper discusses a novel approach to implementing OpenMP on clusters, Traditional approaches to do so rely on Software distributed Shared memory systems to handle shared data. We discuss these and then introduce an alternative approach that translates OpenMP to Global Arrays (GA), explaining the basic strategy. GA requires a data distribution. We do not expect the user to supply this, rather, we show how we perform data distribution and work distribution according to the user-supplied OpenMP static loop schedules. An inspector executor strategy is employed for irregular applications in order to gather information on accesses to potentially non-local data, group non-local data transfers and overlap communications with local computations. Furthermore, a new directive INVARIANT is proposed to provide information about the dynamic scope of data access patterns. This directive can help us generate efficient codes for irregular applications using the inspector executor approach, We also illustrate how to deal with some hard cases containing reshaping and strided accesses during the translation. Our experiments show promising results for the corresponding regular and irregular GA codes. (c) 2005 Elsevier B.V. All rights reserved.

关键词： OpenM/P translation global arrays parallel programming languages distributed memory system

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