Graph data is becoming dynamic and large-scale, demanding high-performance and large-capacity graph storage. Therefore, due to the performance approaching DRAM and the larger capacity than DRAM, persistent memory (PM)...
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ISBN:
(数字)9798331509712
ISBN:
(纸本)9798331509729
Graph data is becoming dynamic and large-scale, demanding high-performance and large-capacity graph storage. Therefore, due to the performance approaching DRAM and the larger capacity than DRAM, persistent memory (PM) has been adopted in large-scale dynamic graph storage systems. However, existing PM-based dynamic graph storage systems have issues, especially PM write amplification caused by the unsorted data structure used to store edges. To improve this issue, we propose a PM-based dynamic graph storage system, HDGraph, using sorted data structure to store edges on DRAM-PM hybrid memory architecture. To better adapt the sorted data structure on PM, HDGraph employs edge buffering on DRAM, merging small writes to reduce write amplification in PM. Moreover, HDGraph also triggers buffer flushing based on a heat evaluating strategy to alleviate DRAM space pressure. Finally, HDGraph maintains a buffering log in PM for edge-level data consistency, enabling quick recovery after a crash. Experimental results show that HDGraph achieves 1.09× to 1.52× higher edge ingestion performance, compared with the only PM-based dynamic graph storage system XPGraph, which use unsorted data structure to store edges.
As an innovative distributed computing technique for sharing the memory resources in high-speed network, RAM Grid exploits the distributed free nodes, and provides remote memory for the nodes which are short of memory...
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As an innovative distributed computing technique for sharing the memory resources in high-speed network, RAM Grid exploits the distributed free nodes, and provides remote memory for the nodes which are short of memory. One of the RAM Grid systems named DRACO, tries to provide cooperative caching to improve the performance of the user node which has mass disk I/O but lacks local memory. However, the performance of DRACO is constrained with the network communication cost. In order to hide the latency of remote memory access and improve the caching performance, we proposed using push- based prefetching to enable the caching providers to push the potential useful memory pages to the user nodes. Specifically, for each caching provider, it employs sequential pattern mining techniques, which adapts to the characteristics of memory page access sequences, on locating useful memory pages for prefetching. We have verified the effectiveness of the proposed method through system analysis and trace-driven simulations.
The authors study multimedia electronic mail together with the issues of concern surrounding it and give an overview of a user-friendly multimedia electronic mail. Based on this study, the authors present a multimedia...
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The authors study multimedia electronic mail together with the issues of concern surrounding it and give an overview of a user-friendly multimedia electronic mail. Based on this study, the authors present a multimedia electronic system that allows the originator to write a scenario to coordinate the parts it sends and to adapt the message restitution to the receiver messaging system.< >
This paper attempts to consolidate the theoretical foundation of the relaxation labeling processes, explore the connections between the relaxation labeling model and the Hopfield associative memory model, and seek for...
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This paper attempts to consolidate the theoretical foundation of the relaxation labeling processes, explore the connections between the relaxation labeling model and the Hopfield associative memory model, and seek for their unification. We start by defining a new labeling assignment space and then formulating relaxation labeling process as a dynamic system of Lyapunov type, which is equipped with a well defined energy function and described by a naturally fitted updating rule. We present consistency condition and show each /spl omega/-limit point of the dynamic system gives a consistent labeling. We finally make a peace between the multilabel and one-label relaxation labeling and reveal an interesting result that, for a one-label case, the newly formulated relaxation labeling model reduces to the Hopfield associative memory model.
Machine learning is currently shifting from a centralized paradigm to decentralized ones where machine learning models are trained collaboratively. In fully decentralized learning algorithms, data remains where it was...
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Machine learning is currently shifting from a centralized paradigm to decentralized ones where machine learning models are trained collaboratively. In fully decentralized learning algorithms, data remains where it was produced, models are trained locally and only model parameters are exchanged among participating entities along an arbitrary network topology and aggregated over time until convergence. Not only this limits the cost of exchanging data but also exploits the growing capabilities of users' devices while mitigating privacy and confidentiality concerns. Such systems are significantly challenged by a potential high-level of heterogeneity both at the system level as participants may have differing capabilities of (e.g., computing power, memory and network connectivity) as well as data heterogeneity (a.k.a non-IIDness). The adoption of fully decentralized learning systems requires designing frugal systems that limit communication, energy and yet ensure convergences. Several avenues are promising from adapting the network topologies to compensate for data heterogeneity to exploiting the high levels of redundancy, both in data and computations, of ML algorithms to limit data and model sharing in such systems.
The Utah Retrieval System Architecture (URSA) was initially developed in 1981 developed as an alternative to central-processor-based information retrieval systems. It combined distributed processing and a windowed use...
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The Utah Retrieval System Architecture (URSA) was initially developed in 1981 developed as an alternative to central-processor-based information retrieval systems. It combined distributed processing and a windowed user interface with a hardware-based search server combined with using document surrogates such as partially-inverted files. The authors have now started the development and testing of a medium-scale (about 10 gigabyte) parallel backend search server to demonstrate its operation and to gather data on the use of such a backend processor in actual operation, including information about query complexity and arrival rates. This searcher, based on a hardware-augmented RISC processor, builds on their experience developing and operating the custom VLSI FSA-based search engine. The use of a programmable processor allows the easy implementation of complex search patterns, such as numeric range matching, while the special hardware augmentation provides considerably better performance than would be available from a standard RISC processor server.< >
To support future command and control (C 2 ) concepts, military telecommunications and information processing must change significantly. Highly automated and integrated communications and processing systems will be re...
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To support future command and control (C 2 ) concepts, military telecommunications and information processing must change significantly. Highly automated and integrated communications and processing systems will be required, which must be able to manage and reconstitute themselves at the network level and the internetwork level if the survivable C 2 architectures required by the military are going to be developed. Emerging technologies in automated communication-resource management, distributed processing, and artificial intelligence (AI) will provide the foundation for building such systems. With these technologies, a battlefield information-management environment can be developed that will readily support distributed, self-managing and self-reconstituting, and, hence, survivable, C 2 . The series of papers presented in this MILCOM '87 session entitled "distributed Systems" were invited to address the theme of survivable command, control and communication (C 3 ). Although one could anticipate a myriad of papers and topics related to such a broad theme, I have selected a series of papers that focus on advanced research and development of technologies related to a conceptual model that I developed as a result of several years of involvement with distributed processing and communications research for tactical and strategic survivable C 3 . This model and its relevance to survivable C 3 are presented in my paper, which introduces the session. This model provides a framework for the six papers that will be presented, which are shown below. 1. "Multi-Destination Protocols for Tactical Radio Networks" by Edgar Caples, Rockwell International. 2.
An electronic neurocomputer, Neuro Turbo, has been implemented, using the recently developed general-purpose, 24-bit floating-point digital signal processor (DSP), MB86220. The Neuro Turbo is a MIMD (multiple-instruct...
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An electronic neurocomputer, Neuro Turbo, has been implemented, using the recently developed general-purpose, 24-bit floating-point digital signal processor (DSP), MB86220. The Neuro Turbo is a MIMD (multiple-instruction-multiple-data) type parallel processor with four ring-coupled DSPs and four dual-port memories. The performance of the Neuro Turbo has been evaluated for several kinds of three-layer neural network. An operational speed of 2 MCPS for the learning process and 11 MCPS for the rewarding process has been achieved.< >
The rapid growth of Internet of Things (IoT) and au-tonomous systems has led to the deployment of edge devices close to the sensing data source for low-latency computation.
ISBN:
(数字)9781665497473
ISBN:
(纸本)9781665497480
The rapid growth of Internet of Things (IoT) and au-tonomous systems has led to the deployment of edge devices close to the sensing data source for low-latency computation.
The sensing coverage of roadside sensing system usually does not cover the entire road network, resulting in block missing values in traffic data. Traditional methods either adopted simple hints or graph neural networ...
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ISBN:
(数字)9798331509712
ISBN:
(纸本)9798331509729
The sensing coverage of roadside sensing system usually does not cover the entire road network, resulting in block missing values in traffic data. Traditional methods either adopted simple hints or graph neural networks to capture the speed variation. However, these methods fail to consider that block missing values have less surrounding values and are less susceptible to the influence of adjacent data. The paper proposes Dynamic Style Transfer-based Generative Adversarial Imputation Network (ST-GAIN) for block missing traffic speed imputation. The core idea is to adopt temporal clustering to abstract a large volume of traffic speed into a series of style data. Subsequently, a dynamic encoding network of latent style codes is performed based on the similarity between the missing speed data and the style data. These style codes are then fed into a style transfer network to guide the imputation of the missing values. Additionally, a style discriminator is used to guide style transfer during training. The experimental results demonstrate that the proposed model outperforms state-of-the-art methods by an average of more than 15% in accuracy.
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